hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 21

• Manufacturer Part Number: hyb18t512160b2fl-5
• Description: 512-mbit Double-data-rate-two Sdram
• Manufacturer: Qimonda

1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
Field
TM
CL
BT
BL
rounding up to the next integer: WR [cycles] ≥ t
for the analogue t
Bits
7
[6:4]
3
[2:0]
Type
w
w
w
w
WR
timing WR
1)
MIN
Description
Test Mode
0
1
CAS Latency
Note: All other bit combinations are illegal.
011
100
101
110
111
Burst Type
0
1
Burst Length
Note: All other bit combinations are illegal.
010
011
B
B
B
B
is determined by t
B
B
B
B
B
B
B
TM Normal Mode
TM Vendor specific test mode
CL 3
CL 4
CL 5
CL 6
CL 7
BT Sequential
BT Interleaved
BL 4
BL 8
WR
(ns) / t
CK.MAX
CK
(ns). The mode register must be programmed to fulfill the minimum requirement
and WR
21
MAX
is determined by t
512-Mbit Double-Data-Rate-Two SDRAM
CK.MIN
HY[B/I]18T512[40/80/16]0B2[C/F](L)
.
WR
Internet Data Sheet
(in ns) by t
CK
(in ns) and