hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet - Page 4

• Manufacturer Part Number: hyb18t512160b2fl-5
• Description: 512-mbit Double-data-rate-two Sdram
• Manufacturer: Qimonda

1) For products released before 01-09-2007.
2) Products released after 01-09-2007 can support
1.2
The 512-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing 536,
870, 912
DRAM. The 512-Mbit device is organized as 32 Mbit ×4 I/O ×4
banks or 16 Mbit ×8 I/O ×4 banks or 8 Mbit ×16 I/O ×4 banks
chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Active Time
Min. Row Cycle Time
Min. Row Cycle Time
Precharge-All (4 banks)
command period
for performance figures.
bits and internally configured as a quad-bank
Description
CL3
CL4
CL5
CL6
DDR2
f
f
f
f
t
t
t
t
t
t
t
CK3
CK4
CK5
CK6
RCD
RP
RAS
RAS
RC
RC
PREA
–800D
5–5–5
–25F
200
266
400
–
12.5
12.5
45
40
57.5
52.5
12.5
t
RAS.MIN
= 40 ns for all DDR2 speed sort.
–2.5
–800E
6–6–6
200
266
333
400
15
15
45
40
60
55
15
4
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16 bit address bus for ×4 and ×8 organised components is
used to convey row, column and bank address information in
a RAS-CAS multiplexing style.
A 15 bit address bus for ×16 components is used to convey
row, column and bank address information in a RAS-CAS
multiplexing style.
The DDR2 device operates with a 1.8 V
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
–3
–667C
4–4–4
200
333
333
–
12
12
45
40
57
52
12
–667D
5–5–5
–3S
200
266
333
–
15
15
45
40
60
55
15
512-Mbit Double-Data-Rate-Two SDRAM
HY[B/I]18T512[40/80/16]0B2[C/F](L)
–3.7
–533C
4–4–4
200
266
266
–
15
15
45
40
60
55
15
–5
–400B
3–3–3
200
200
–
–
15
15
40
40
55
55
15
Performance Table
Internet Data Sheet
t
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
Unit
CK
TABLE 1
±
0.1 V power
Note
1)
2)
1)
2)