74ABT374CSCX Fairchild Semiconductor, 74ABT374CSCX Datasheet - Page 2
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74ABT374CSCX
Manufacturer Part Number
74ABT374CSCX
Description
IC FLIP FLOP OCT D-TYPE 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74ABTr
Type
D-Type Busr
Datasheet
1.74ABT374CSJ.pdf
(13 pages)
Specifications of 74ABT374CSCX
Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
200MHz
Delay Time - Propagation
3.2ns
Trigger Type
Positive Edge
Current - Output High, Low
32mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Logic Family
ABT
Technology
BiCMOS
Number Of Bits
8
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
5V
Package Type
SOIC W
Propagation Delay Time
7.6ns
Low Level Output Current
64mA
High Level Output Current
-32mA
Frequency (max)
150MHz
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT374CSCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
Connection Diagram
Functional Description
The ABT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the con-
tents of the eight flip-flops are available at the outputs.
When OE is HIGH, the outputs are in a high impedance
state. Operation of the OE input does not affect the state
of the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
2
Pin Descriptions
Function Table
H
L
X
Z
NC
D
CP
OE
O
Pin Names
OE CP D
0
0
H
H
H
H
L
L
L
L
–D
–O
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
Inputs
LOW-to-HIGH Transition
No Change
7
7
H
H
H
H
H
H
H
H
L
L
L
L
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-STATE Output Enable Input
(Active LOW)
3-STATE Outputs
Internal Outputs
NC
NC
NC
NC
Q
H
H
L
L
Description
NC
NC
O
Z
Z
Z
Z
H
L
Hold
Hold
Load
Load
Data Available
Data Available
No Change in
Data
No Change in
Data
Function
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