hm62g18512 Renesas Electronics Corporation., hm62g18512 Datasheet
hm62g18512
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hm62g18512 Summary of contents
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... Synchronous Fast Static RAM Description The HM62G18512 is a synchronous fast static RAM organized as 512-kword speed access time by employing the most advanced CMOS process and high speed circuit designing technology most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system ...
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... HM62G18512 Series Ordering Information Type No. Access time HM62G18512BP-4 2.1 ns HM62G18512BP-5 2.5 ns Pin Arrangement 2 Cycle time Package 4.0 ns 119-bump 5 119-bumps BGA VDDQ SA0 SA6 NC SA4 SA2 VDDQ SA7 NC SA8 SA18 SA13 SA3 VDD SA5 SA1 NC D DQb0 NC ...
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... Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection Protocol Synchronous register to register operation via a resistance RQ where 150 HM62G18512 Series Notes 2... 2...8 Notes 2 RQ 300 ...
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... HM62G18512 Series Block Diagram A18 R-Add register JTAG register SS SS register JTAG register SWE SWE register JTAG register 2 SWEx SWEx register JTAG register G JTAG register K K JTAG register ZZ JTAG register V REF JTAG register ZQ JTAG register TDI JTAG tap TCK controller ...
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... Operation sleep mode L-H H-L Dead (not selected) Dead (Dummy read) L-H H-L Read L L-H H-L Write a, b byte H L-H H-L Write a byte L L-H H-L Write b byte . Under such single-ended clock operation, all parameters REF HM62G18512 Series DQ ( High-Z High-Z High-Z High-Z High-Z Dout (a,b)0-8 High-Z Din (a,b)0-8 High-Z Din (a)0-8 High-Z Din (b)0-8 5 ...
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... HM62G18512 Series Absolute Maximum Ratings Parameter Input voltage on any pin Core supply voltage Output supply voltage Operating temperature Storage temperature Junction temperature Output short–circuit current Latch up current Package junction to case thermal resistance Package junction to ball thermal resistance Notes: 1. All voltage is referred ...
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... Min Typ V 3.135 3. 1.4 1.5 DDQ 0.65 0.75 REF 0.1 — IH REF V –0.5 — 0.1 — DIF V 0.55 — CM may not exceed REF V CM HM62G18512 Series Max Unit Notes 3. DDQ V – 0 REF DDQ 0. REF 7 ...
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... HM62G18512 Series DC Characteristics ( [Tj max = 110 C], V Parameter Symbol Min Input leakage current I — LI Output leakage current I — LO Standby current I — SBZZ V operating current, I — DD DD4 excluding output drivers 4 ns cycle V operating current, I — DD DD5 excluding output drivers 5 ns cycle ...
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... Output driver supply voltage: V Output load: See figure 16.7 16.7 DQ 16.7 Symbol Min C — — CLK C — 0.75 V REF = 1.5 V DDQ 0.75 V HM62G18512 Series Max Unit Note 3.3 V +10%, –5%) = – ...
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... HM62G18512 Series Single Differential Clock Register-Register Mode ( Parameter CK clock cycle time CK clock high width CK clock low width Address setup time Data setup time Address hold time Data hold time Clock high to output valid Clock high to output hold Clock high to output valid ...
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... Timing Waveforms Read Cycle SWE SWEx DQ Note KHKH KHKL KLKH t t AVKH KHAX AVKH KHAX t t AVKH KHAX t KHQX KHQV IL HM62G18512 Series ...
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... HM62G18512 Series Read Cycle-2 (SS Controlled SWE SWEx DQ Note KHKH KHKL KLKH t t AVKH KHAX AVKH KHAX t t AVKH KHAX t KHQZ KHQX2 ...
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... Read Cycle-3 (G Controlled) t KHKH SWE SWEx G DQ Note KHKL KLKH t t AVKH KHAX AVKH KHAX t t AVKH KHAX t GHQZ HM62G18512 Series A4 t GLQV GLQX 13 ...
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... HM62G18512 Series Write Cycle SWE SWEx Note KHKH KHKL KLKH t t AVKH KHAX AVKH KHAX t t AVKH KHAX t t AVKH KHAX t t DVKH KHDX ...
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... SWE SWEx ZZ Sleep active DQ t ZZR Note WRITE READ DEAD (SS control) t KLKH t t AVKH KHAX KHAX t KHAX GLQV t DVKH KHDX GHQZ GLQX t KLKH Sleep off Do 1 HM62G18512 Series WRITE KHQZ Sleep active t ZZE 15 ...
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... HM62G18512 Series Boundary Scan Test Access Port Operations In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series contains a TAP controller ...
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... THTL t 30 TLTH t 10 MVTH t 10 THMX DVTH t 10 THDX t 0 TLQX t — TLQV TDO HM62G18512 Series Max Unit Note — ns — ns — ns — ns — ns — — — ns — ns — 1 ...
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... HM62G18512 Series TAP Controller Timing Diagram t THTH TCK t MVTH TMS TDI TDO RAM Address Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register THTL TLTH t THMX t t DVTH THDX t TLQV t TLQX Length Symbol 3 bits IR [0 ...
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... BYPASS BYPASS Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. HM62G18512 Series Operation Tristate all data drivers and capture the pad value Tristate all data drivers and capture the pad value 19 ...
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... HM62G18512 Series Boundary Scan Order Bit No. Bump Notes: 1. Bit number1 is the first scan bit to exit the chip. ...
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... Width Use in the future 1 Select- DR-Scan 0 1 Capture- Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- HM62G18512 Series Vendor ID No. 1 Select- IR-Scan 0 1 Capture- Shift-IR ...
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... HM62G18512 Series Package Dimensions HM62G18512BP Series (BP-119A) 14.00 4 C1.2 Pin 1 Index B 13.0 0.10 119 0.75 0. Details of the part 1.27 Hitachi Code JEDEC EIAJ Mass (reference value) Unit BP-119A Conforms — ...
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... Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160 HM62G18512 Series Hitachi Asia Ltd. Hitachi Asia (Hong Kong) Ltd. 16 Collyer Quay #20-00 Group III (Electronic Components) Hitachi Tower 7th Flr, North Tower, World Finance Centre, ...