hm62g18512 Renesas Electronics Corporation., hm62g18512 Datasheet - Page 16

• Manufacturer Part Number: hm62g18512
• Description: 8m Synchronous Fast Static Ram 512k-word X 18-bit - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

HM62G18512 Series
Boundary Scan Test Access Port Operations
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 -
1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series
contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.
Test Access Port Pins
Symbol I/O
TCK
TMS
TDI
TDO
Note: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
TAP DC Operating Conditions (Ta = 0 to 70 C, [Tj max = 110 C])
Parameter
Boundary scan input high voltage
Boundary scan input low voltage
Boundary scan input leakage current
Boundary scan output low voltage
Boundary scan output high voltage
Notes: 1. 0
16
To disable the TAP, TCK must be connected to V
To test Boundary scan, ZZ pin need to be kept below V
2. I
3. I
OL
OH
= 8 mA.
= –8 mA.
Vin
V
DD
for all logic input pin.
Name
Test clock
Test mode select
Test data in
Test data out
Symbol
V
V
I
V
V
LI
IH
IL
OL
OH
SS
. TDO should be left unconnected.
REF
Min
2.0
–0.5
–2
—
2.4
– 0.4 V.
Max
V
0.8
2
0.4
—
DD
+ 0.3 V
Unit
V
V
V
A
Notes
1
2
3