at17lv020 ATMEL Corporation, at17lv020 Datasheet - Page 3

• Manufacturer Part Number: at17lv020
• Description: 2-megabit Fpga Configuration Eeprom Memory
• Manufacturer: ATMEL Corporation

Condition 1
Condition 2
Cascading Serial
Configuration
EEPROMs
AT17 Series Reset
Polarity
The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE
in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an
external reset condition during the configuration cycle. If a system reset is applied to the
FPGA, it will abort the original configuration and then reset itself for a new configuration,
as intended. Of course, the AT17 Series Configurator does not see the external reset
signal and will not reset its internal address counters and, consequently, will remain out
of sync with the FPGA for the remainder of the configuration cycle.
Note:
Figure 1. Condition 2 Connection
Notes:
The FPGA CON pin drives only the CE input of the AT17 Series Configurator, while the
OE input is driven by the FPGA INIT pin (Figure 1). This connection works under all nor-
mal circumstances, even when the user aborts a configuration before CON has gone
High. A Low level on the RESET/OE
rator’s internal address pointer, so that the reconfiguration starts at the beginning.
Note:
The AT17 Series Configurator does not require an inverter for either condition since the
RESET polarity is programmable.
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger
configuration memories, cascaded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock signal to the Configurator
asserts its CEO output Low and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded Configurators are
reset if the RESET/OE on each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon completion, then the RESET/OE inputs
can be tied to its inactive (default Low) level. For more details on programming the
EEPROM’s reset polarity, please reference “Programming Specification for Atmel’s
FPGA Configuration EEPROMs”.
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry standard programmer
algorithms. For more details on programming the EEPROM’s reset polarity, please ref-
RESET
1. For this condition, the reset polarity of the EEPROM must be set active High.
1. Use of the READY pin is optional.
2. Reset polarity must be set to active Low.
1. For this condition, the reset polarity of the EEPROM must be set active Low.
GND
M2
M1
M0
RESET
AT40K
CCLK
D<0>
CON
(1)
INIT
input – during FPGA reset – clears the Configu-
DATA
CLK
CE
RESET/OE
AT17C/LV020
SER_EN
READY
VCC
(1)
3