at17lv020 ATMEL Corporation, at17lv020 Datasheet - Page 4

• Manufacturer Part Number: at17lv020
• Description: 2-megabit Fpga Configuration Eeprom Memory
• Manufacturer: ATMEL Corporation

Programming Mode
Standby Mode
Pin Configurations
4
20-pin
PLCC
10
14
15
17
20
2
4
6
8
AT17C/LV020
RESET/OE
SER_EN
READY
Name
DATA
GND
CEO
VCC
CLK
CE
A2
I/O
I/O
O
O
I
I
I
I
I
erence the “Programming Specification for Atmel’s FPGA Configuration EEPROMs”
application note.
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. See the “Programming
Specification for Atmel's FPGA Configuration EEPROMs” application note for further
information. The AT17C parts are read/write at 5V nominal. The AT17LV parts are
read/write at 3.3V nominal.
The AT17C/LV020 enters a low-power standby mode whenever CE is asserted High. In
this mode, the Configurator consumes less than 0.5 mA of current at 5.0 volts with
CMOS level inputs. The output remains in a high impedance state regardless of the
state of the OE input.
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low-power standby mode. Note that this pin will not enable/disable the device in
the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read
from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until
OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low; see the “Programming Specification” application note for more
details).
Open collector reset state indicator. Driven Low during power-up reset, released when power-
up is complete. (Recommend a 4.7 KΩ pull-up on this pin if used).
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
+3.3V/+5V power supply pin.
Description