s1f78520 Epson Electronics America, Inc., s1f78520 Datasheet - Page 10

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s1f78520

Manufacturer Part Number
s1f78520
Description
Charge-pump Step Down Regulator With Power Saving Mode
Manufacturer
Epson Electronics America, Inc.
Datasheet
S1F78520
10
Power good detection circuit
Power good signals are detected when both of the output pins V
voltage.
As for the power good detection range, provision of a hysteresis width for the lower limit value of detection
according to Fig. 5 indicated below is effective to prevent occurrences of unstable power good signal outputs in
the neighborhood of the detection limit value range.
Also, delay setting can be made for the power good signals by use of the capacitor CDPG and the resistor
RDPG. When the output voltage rises beyond the cancelling voltage, charge to the external capacitor will
begin. When the capacitor voltage rises beyond the delaying threshold valve voltage, the power good signal
changes from the V
The delaying time can be calculated by formula 5.
Fig. 6 is an outline drawing for delay settings and Fig. 7 is the connection diagram in the neighborhood of the
power good detection circuit.
SS
*
Power good detection
level to open state.
voltage setting
Fig. 5 Power good detecting range
Cancellation
(No good)
Lower limit of detection
(Power good)
OUT1
Hysteresis width: 1%
and V
OUT2
are satisfying the specified
Rev. 1.2

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