lm5039mhx National Semiconductor Corporation, lm5039mhx Datasheet - Page 12

• Manufacturer Part Number: lm5039mhx
• Description: Half-bridge Pwm Controller With Average Current Limit
• Manufacturer: National Semiconductor Corporation

www.national.com
Current Limit
The LM5039 utilizes two high-speed comparators to imple-
ment a current limiting in an overload condition: A higher
threshold (600mV) comparator is used to implement a fast
peak cycle-by-cycle current limit to provide instantaneous
protection to the power converter and a lower threshold
(500mV) comparator is used to implement a slower average
current limit that balances the half-bridge capacitor divider
voltage. During an overload event, average current limit
scheme allows the power converter to act as a constant cur-
rent source with the duty cycle maintained such that the
average output current is:
This scheme is often known as “brickwall” current limiting or
constant current limiting and its response is same whether the
The CS pin is driven by a signal representative of the primary
current. During a continuous overload event, the 500mV com-
parator sources pulses of current into the average current limit
pin (ACL). A capacitor connected to the ACL pin smooths and
averages the pulses. When the ACL capacitor is charged to
approximately 2V, it starts pulling down the PWM comparator
input via the current mirror shown in
event persists, the ACL takes control of the duty cycle through
the PWM comparator, instead of peak cycle-by-cycle control.
The average current limiting can be disabled by shorting the
ACL pin to GND.
FIGURE 2. Peak Cycle-by-Cycle and Average Current Limit Circuitry
Figure
2. As the overload
12
load is a soft-short or a hard-short. Typically, in an overload
condition, the PWM cycle is terminated by the peak cycle-by-
cycle comparator instead of the PWM comparator. This is
similar to peak current mode control, which inherently results
in an on-time imbalance between the two phases of a half-
bridge topology. Any such imbalance, for an extended period
of time, will cause the voltage at the center point of the ca-
pacitor divider to drift either towards the input voltage or
ground. However, in an average current limit scheme, the
PWM cycle is terminated through the PWM comparator, by
pulling down the PWM control input. Because of its averaging
nature, the PWM control voltage is essentially held at a con-
stant dc voltage. Therefore, the on-time of successive PWM
cycles are equal, thus maintaining balance of the center-point
of the capacitor divider.
A small R-C filter connect to the CS pin and located near the
controller is recommended to suppress noise. An internal
36Ω MOSFET connected to the CS input discharges the ex-
ternal current sense filter capacitor at the conclusion of every
cycle. The discharge MOSFET remains on for an additional
50 ns after the HO or LO driver switches high to blank leading
edge transients in the current sensing circuit. Discharging the
CS pin filter each cycle and blanking leading edge spikes re-
duces the filtering requirements and improves the current
sense response time.
30100515