lm5039mhx National Semiconductor Corporation, lm5039mhx Datasheet - Page 15

• Manufacturer Part Number: lm5039mhx
• Description: Half-bridge Pwm Controller With Average Current Limit
• Manufacturer: National Semiconductor Corporation

an 124 kΩ to approximate the desired 58.6µs time constant.
If load transient response is slowed by the 10% margin, the
R
be slightly decreased by increasing R
Oscillator, Sync Capability
The LM5039 oscillator frequency is set by a single external
resistor connected between the RT and AGND pins. To set a
desired oscillator frequency, the necessary RT resistor is cal-
culated from:
For example, if the desired oscillator frequency is 400kHz (HO
and LO each switching at 200 kHz) a 24.9kΩ resistor would
be the nearest standard one percent value.
Each output (HO, LO, SR1 and SR2) switches at half the os-
cillator frequency. The voltage at the RT pin is internally
regulated to a nominal 2V. The RT resistor should be located
as close as possible to the IC, and connected directly to the
pins (RT and AGND). The tolerance of the external resistor,
and the frequency tolerance indicated in the Electrical Char-
acteristics, must be taken into account when determining the
worst case frequency range.
The LM5039 can be synchronized to an external clock by ap-
plying a narrow pulse to the RT pin. The external clock must
be at least 10% higher than the free-running oscillator fre-
quency set by the RT resistor. If the external clock frequency
is less than the RT resistor programmed frequency, the
LM5039 will ignore the synchronizing pulses. The synchro-
nization pulse width at the RT pin must range between 15ns
to 150ns. The clock signal should be coupled into the RT pin
through a 100 pF capacitor. When the synchronizing pulse
transitions low-to-high (rising edge), the voltage at the RT pin
must be driven to exceed 3.2V volts from its nominal 2 VDC
level. During the clock signal’s low time, the voltage at the RT
pin will be clamped at 2 VDC by an internal regulator. The
output impedance of the RT regulator is approximately
100Ω. The RT resistor is always required, whether the oscil-
lator is free running or externally synchronized.
Gate Driver Outputs (HO & LO)
The LM5039 provides two alternating gate driver outputs, the
floating high side gate driver HO and the ground referenced
FF
value can be increased. The system signal-to-noise will
FF
x C
FF
.
15
low side driver LO. Each driver is capable of sourcing 1.25A
and sinking 2A peak. The HO and LO outputs operate in an
alternating manner, at one-half the internal oscillator frequen-
cy. The LO driver is powered directly by the VCC regulator.
The HO gate driver is powered from a bootstrap capacitor
connected between HB and HS. An external diode connected
between VCC (anode pin) and HB (cathode pin) provides the
high side gate driver power by charging the bootstrap capac-
itor from VCC when the switch node (HS pin) is low. When
the high side MOSFET is turned on, HB rises to a peak volt-
age equal to V
The HB and VCC capacitors should be placed close to the
pins of the LM5039 to minimize voltage transients due to par-
asitic inductances since the peak current sourced to the MOS-
FET gates can exceed 1.25A. The recommended value of the
HB capacitor is 0.01 µF or greater. A low ESR / ESL capacitor,
such as a surface mount ceramic, should be used to prevent
voltage droop during the HO transitions.
The maximum duty cycle for each output is equal to or slightly
less than 50% due to a programmed sync rectifier delay. The
programmed sync rectifier delay is determined by the DLY pin
resistor. If the COMP pin is open circuit, the outputs will op-
erate at maximum duty cycle. The maximum duty cycle for
each output can be calculated with the following equation:
Where T
HO or LO outputs, T1 is the programmed sync rectifier delay.
For example, if the oscillator frequency is 200 kHz, each out-
put will cycle at 100 kHz (T
delay, the maximum duty cycle at this frequency is calculated
to be 50%. Using a programmed sync rectifier delay of 100
ns, the maximum duty cycle is reduced to 49%. Because there
is no fixed deadtime in LM5039, it is recommended that the
delay pin resistor be not less than 10k. Internal delays, which
are not guaranteed, are the only protection against cross con-
duction if the programmed delay is zero, or very small.
S
is the period of one complete cycle for either the
VCC
+ V
HS
where V
S
= 10 µs). Using no programmed
HS
is the switch node voltage.
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