x9520v20iz-bt1 Intersil Corporation, x9520v20iz-bt1 Datasheet
x9520v20iz-bt1
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x9520v20iz-bt1 Summary of contents
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... X9520V20IZ-AT2* (Note) X9520V ZIA X9520V20IZ-B (Note) X9520V ZIB X9520V20IZ-BT1* (Note) X9520V ZIB * Please refer to TB347 for details on reel specifications. ** For details, see DC Operating characteristics NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Block Diagram WP DATA REGISTER SDA COMMAND DECODE & SCL CONTROL LOGIC THRESHOLD RESET LOGIC V1/VCC Detailed Device Description The X9520 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, V1/VCC power-on reset control, V1/VCC low voltage reset ...
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Pinout Pin Descriptions TSSOP NAME 1 R Connection to end of resistor array for (the 256 Tap) DCP Connection to terminal equivalent to the “Wiper” mechanical potentiometer for DCP Connection ...
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Pin Descriptions (Continued) TSSOP NAME 19 V1RO V1/VCC RESET Output. This is an active HIGH, open drain output which becomes active whenever V1/VCC falls below V . V1RO becomes active on power-up and remains active for a time t TRIP1 ...
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SCL SCL from Master from Master Data Output from Transmitter Data Output from Receiver START FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER SERIAL ACKNOWLEDGE An ACKNOWLEDGE (ACK software convention used to indicate a successful data transfer. The transmitting device, ...
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SA7 SA6 SA5 SA4 SA3 SA2 INTERNAL DEVICE TYPE DEVICE IDENTIFIER ADDRESS INTERNAL ADDRESS INTERNALLY ADDRESSED (SA3 - SA1) DEVICE 000 EEPROM Array 010 CONSTAT Register 111 BIT SA0 OPERATION 0 1 FIGURE 4. SLAVE ADDRESS ...
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V1/VCC t trans 0 At both ends of each array and between each resistor segment there is a CMOS switch connected to the wiper (R ) output. Within each individual array, only one switch w x may be turned on ...
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WRITE TYPE † WT DESCRIPTION 0 Select a Volatile Write operation to be performed on the DCP pointed to by bits P1 and P0 1 Select a Nonvolatile Write ...
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Therefore, the Data Byte 00001111 (15 corresponds to setting the “wiper terminal” to tap position 15. Similarly, the Data Byte 00011100 (28 setting the “wiper terminal” to tap position 28. The mapping of the Data Byte to “wiper position” ...
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Signals from the Master SDA Bus Signals from the Slave It should be noted that when reading out the data byte for DCP0 (64 Tap), the upper two most significant bits are “unknown” bits. For DCP1 (100 Tap), the upper ...
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BYTES FIGURE 13. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11. SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE EEPROM Array Read Operations Read operations are initiated in the same manner as write ...
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S t Signals from the a Master r t SDA Bus 1 0 Signals from the Slave the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition (Refer to Figure 15.). A similar operation called ...
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CS3 CS7 CS6 CS4 CS5 POR1 V2OS V3OS BL1 BL0 BIT(S) DESCRIPTION WEL Write Enable Latch bit RWEL Register Write Enable Latch bit V2OS V2 Output Status flag V3OS V3 Output Status flag BL1 - BL0 Sets ...
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SCL SDA SLAVE ADDRESS BYTE T FIGURE 18. CONSTAT REGISTER WRITE COMMAND SEQUENCE The nominal Power-on Reset delay time can be selected from the following table, by writing the ...
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S t Signals from the a Master r t SDA Bus Signals from the Slave Data Protection There are a number of levels of data protection features designed into the X9520. Any write ...
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X9520 Write Permission Status BLOCK LOCK BITS DCP VOLATILE WRITE BL0 BL1 WP PERMITTED YES YES Vx VxRO ...
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Pin WP must then be brought LOW to complete the operation (See Figure 23).The user does not have to set the WEL bit in the CONSTAT register before performing this write sequence. After being reset, the ...
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V1/VCC). The input voltage is decreased, and found to trip the associated output level of pin V2RO from a LOW to a HIGH, when V2 reaches 3.09 V. From this, it can be calculated that the programming ...
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Absolute Maximum Ratings Temperature under Bias .-65 to +135°C Voltage on WP pin (With respect to Vss) . ...
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AC Characteristics (See Figure 27, Figure 28, Figure 29) SYMBOL f SCL Clock Frequency SCL t (Note 5) Pulse width Suppression Time at inputs IN t (Note 5) SCL LOW to SDA Data Out Valid AA t Time the bus ...
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Potentiometer Characteristics SYMBOL PARAMETER R End to End Resistance Tolerance TOL V R Terminal Voltage (x = 0,1,2) RHx Terminal Voltage (x = 0,1,2) RLx L P Power Rating (Note 1) (Note DCP Wiper ...
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V1RO, V2RO, V3RO Output Timing. SYMBOL DESCRIPTION t (Note 5) Power On Reset delay time PURST t (Figure 31 V1RO propagation delay MRD (Note 2) (Note 5) t (Note 5) MR pulse width MRDPW t (Note 5) V1/VCC, ...
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START SCL SDA IN t SU:WP WP SCL 8th BIT OF LAST BYTE SDA t R V1/VCC 0V t PURST V1RO FIGURE 30. POWER-UP AND POWER-DOWN TIMING 23 X9520 Clk 1 Clk 9 t HD:WP FIGURE 28. ...
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MR 0V V1RO 0V V1/VCC RPDx VxRO V1/VCC Note : x = 2,3. 24 X9520 t MRPW t MRD FIGURE 31. MANUAL RESET TIMING DIAGRAM t t RPDx RPDx FIGURE 32. V2, V3 TIMING DIAGRAM t ...
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V1/VCC, V2 TSU VPS SCL SDA NOTE : V1/VCC must be greater than V2, V3 when programming. FIGURE 33. V Rwx (x = 0,1,2) R wx( tap position SCL SDA 1 0 ...
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Appendix 1 DCP1 (100 Tap) Tap Position to Data Byte Translation Table TAP POSITION DECIMAL ...
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Appendix 2 DCP1 (100 Tap) Tap Position to Data Byte Translation Algorithm Example. (Example 1) unsigned DCP1_TAP_Position(int tap_pos) { int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); ...
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APPENDIX 2 DCP1 (100 TAP) TAP POSITION TO DATA BYTE TRANSLATION ALGORITHM EXAMPLE. (EXAMPLE 2) unsigned DCP100_TAP_Position(int tap_pos optional range checking */ if (tap_pos < 0) return ((unsigned)0); else if (tap_pos >99) return ((unsigned) 96); /* 100 Tap ...
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