x9520v20iz-bt1 Intersil Corporation, x9520v20iz-bt1 Datasheet - Page 6

• Manufacturer Part Number: x9520v20iz-bt1
• Description: Fiber Channel/gigabit Ethernet Laser Diode Control For Fiber Optic Modules Triple Dcp, Por, 2kbit Eeprom Memory, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either the
EEPROM array, the Non Volatile Memory of a DCP (NVM),
or the CONSTAT Register) has been correctly issued
(including the final STOP condition), the X9520 initiates an
internal high voltage write cycle. This cycle typically requires
5 ms. During this time, no further Read or Write commands
can be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a START
condition followed by a Slave Address Byte. The Slave
Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set to
either 1 or 0 in this case. If the device is still busy with the
high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation, an
ACKNOWLEDGE will be returned and the host can then
proceed with a read or write operation (Refer to Figure 5.).
Digitally Controlled Potentiometers
DCP Functionality
The X9520 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 0,1,2).
INTERNAL ADDRESS
SA7
1 0 1 0
DEVICE TYPE
(SA3 - SA1)
IDENTIFIER
FIGURE 4. SLAVE ADDRESS FORMAT
BIT SA0
SA6
000
010
111
0
1
SA5
SA4
INTERNALLY ADDRESSED
6
SA3
CONSTAT Register
INTERNAL
ADDRESS
EEPROM Array
DEVICE
OPERATION
SA2
DEVICE
WRITE
DCP
READ
SA1
Hx
and R
READ/
WRITE
R/W
SA0
Lx
X9520
REGISTER
VOLATILE
COUNTER
MEMORY
WIPER
(WCR)
(NVM)
FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
NON
FIGURE 6. DCP INTERNAL STRUCTURE
command sequence?
Byte load completed
Issue Slave Address
Byte (Read or Write)
complete. Continue
High Voltage Cycle
command sequence
Enter ACK Polling
by issuing STOP.
Continue normal
Issue START
Read or Write
PROCEED
returned?
DECODER
ACK
YES
YES
N
2
1
0
SWITCHES
“WIPER”
FET
NO
NO
I
ssue STOP
RESIST OR
ARRA Y
Issue STOP
August 20, 2007
FN8206.2
R
R
R
Hx
Lx
Wx