hip6016cb Intersil Corporation, hip6016cb Datasheet - Page 8

• Manufacturer Part Number: hip6016cb
• Description: Advanced Pwm And Dual Linear Power Control
• Manufacturer: Intersil Corporation

latch. A sequence of three over-current fault signals also
sets the fault latch. A comparator indicates when C
charged (UP signal), such that an under-voltage event on
either linear output (VSEN2 or VSEN3) is ignored until after
the soft-start interval (T4 in Figure 6). At start-up, this allows
V
Cycling the bias input voltage (+12V
then on resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V
fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents. The
PWM controller uses the upper MOSFET’s on-resistance,
r
outputs. The linear regulator monitors the current of the
integrated power device and signals an over-current condition
for currents in excess of 180mA. Additionally, both the linear
regulator and the linear controller monitor VSEN2 and VSEN3
for under-voltage to protect against excessive currents.
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the output inductor (L
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (I
R
capacitor (C
counter. C
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
LUV
OC1
DS(ON)
OV
OUT2
SS
OCSET
0.15V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
and V
. This inhibits all outputs, discharges the soft-start
to monitor the current for protection against shorted
OUT1
SS
+
-
+
-
D
SS
OUT3
recharges at T2 and initiates a soft-start cycle
•
) with a 11 A current sink, and increments the
to increase. When the output exceeds the
r
DS(ON)
CURRENT
UP
LATCH
OVER
S
R
to slew up over increased time intervals.
Q
) exceeds the level programmed by
POR
2-203
R
COUNTER
IN
S
on the VCC pin) off
INHIBIT
LATCH
FAULT
S
R
OUT1
OUT1
OUT1
Q
SS
). At time
is
VCC
. The
is fully
FAULT
HIP6016
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments
to 3. This sets the fault latch to disable the converter. The fault
is reported on the FAULT pin.
The linear regulator operates in the same way as PWM to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause VSEN2 or VSEN3
to fall below the linear under-voltage threshold, the LUV
signal sets the over-current latch if C
Blanking the LUV signal during the C
the linear outputs to build above the under-voltage threshold
during normal start-up. Cycling the bias input power off then
on resets the counter and the fault latch.
OVER-CURRENT TRIP: V
(i
D
CURRENT1
OC1
HIP6016
• r
10V
OVER-
4V
2V
0A
0V
0V
DS(ON)
PWM
+
-
FIGURE 8. OVER-CURRENT OPERATION
t0
FIGURE 9. OVER-CURRENT DETECTION
> I
COUNT
CONTROL
OCSET
= 1
t1
OVERLOAD
GATE
APPLIED
• R
DRIVE
OCSET
I
DS
OCSET
200 A
t2
> V
)
SET
COUNT
VCC
VCC
TIME
= 2
REPORTED
OCSET
UGATE
PHASE
LGATE
PGND
FAULT
SS
SS
charge interval allows
is fully charged.
t3
V
V
R
OCSET
PHASE
OCSET
V
SET
COUNT
+
= 3
= V
= V
t4
V
IN
IN
IN
i
D
+
- V
- V
V
= +5V
DS
SET
DS