emc1428 Standard Microsystems Corp., emc1428 Datasheet - Page 16

• Manufacturer Part Number: emc1428
• Description: 1 Degree C Multiple Temperature Sensor With Hw Thermal Shutdown
• Manufacturer: Standard Microsystems Corp.

Revision 0.68 (07-08-08)
4.1
4.1.1
4.1.2
4.2
ALERT Output
SYS_SHDN Output
The ALERT pin is an open drain output and has two modes of operation: interrupt mode and
comparator Mode. The mode of the ALERT output is selected via the ALERT / COMP bit in the
Configuration Register.
ALERT Pin Interrupt Mode
When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit
measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected.
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are
cleared. Each channel is subject to the fault queue (see
The ALERT pin can be masked by setting the MASK bit. Once the ALERT pin has been masked, it
will be de-asserted and remain de-asserted until the MASK bit is cleared by the user. Any interrupt
conditions that occur while the ALERT pin is masked will update the Status Register normally.
The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more ALERT outputs can be hard-wired
together.
ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in comparator mode it will be asserted if any of the
measured temperatures meets or exceeds the respective high limit or drops below the respective low
limit. The ALERT pin will remain asserted until all temperatures drop below the corresponding high
limit minus the THERM Hysteresis value.
When the ALERT pin is asserted in comparator mode, the corresponding status bits will be set.
Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK bit will not block the ALERT pin in this mode, however the individual channel masks (see
Section
channel is subject to the fault queue (see
The SYS_SHDN output is asserted independently of the ALERT output and cannot be masked. If the
External Diode 1 temperature exceeds the Hardware Critical / Thermal Shutdown Limit for the
programmed number of consecutive measurements, then the SYS_SHDN pin is asserted.
The Hardware Critical / Thermal Shutdown Limit is defined by the TRIP_SET pin as described in
Section
In addition to External Diode 1 channel triggering the SYS_SHDN pin when the measured temperature
exceeds to the Hardware Critical / Thermal Shutdown Limit, each of the temperature measurement
channels can be configured to assert the SYS_SHDN pin when they exceed the corresponding
THERM Limit.
When the SYS_SHDN pin is asserted, it will not release until the External Diode 1 temperature drops
below the Hardware Thermal Shutdown Limit minus 10°C and all other measured temperatures drop
below the THERM Limit minus the THERM Hysteresis value (when linked to SYS_SHDN).
The External Diode 1 channel and any software enabled channels are subject to the fault queue such
that the error must exceed the threshold for one to four consecutive measurements before the
SYS_SHDN pin is asserted.
Figure 4.2
pin.
4.3.
5.13) will prevent the respective channel from asserting the ALERT pin. In addition, each
shows a block diagram of the interaction between the input channels and the SYS_SHDN
1°C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones
DATASHEET
Section
16
5.14).
Section
5.14).
SMSC EMC1428
Datasheet