pic24hj128gp510at-i-pt Microchip Technology Inc., pic24hj128gp510at-i-pt Datasheet - Page 219

• Manufacturer Part Number: pic24hj128gp510at-i-pt
• Description: High-performance, 16-bit Microcontrollers
• Manufacturer: Microchip Technology Inc.

21.0
PIC24HJXXXGPX06A/X08A/X10A
several features intended to maximize application flex-
ibility and reliability, and minimize cost through elimina-
tion of external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 21-1:
© 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Address
Note:
programming capability
Note 1: When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.
2: When read, this bit returns the current programmed value.
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC24HJXXXGPX06A/X08A/X10A
families of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 23.
“CodeGuard™ Security” (DS70239),
Section 24. “Programming and Diag-
nostics” (DS70246), and Section 25.
“Device Configuration” (DS70231) in
the “PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
Name
DEVICE CONFIGURATION REGISTER MAP
FWDTEN
IESO
Bit 7
—
—
FCKSM<1:0>
Reserved
RBS<1:0>
RSS<1:0>
PIC24HJXXXGPX06A/X08A/X10A
devices
Reserved
WINDIS
(1)
Bit 6
—
—
(2)
include
Preliminary
PLLKEN
JTAGEN
Bit 5
—
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
21.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 21-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT and FPOR
Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
WDTPRE
Bit 4
—
—
—
—
—
—
—
Configuration Bits
Bit 3
—
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
1111’. This makes them
—
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
DS70592A-page 217
Bit 1
ICS<1:0>
GWRP
BWRP
SWRP
Bit 0