atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 163
atmega32c1
Manufacturer Part Number
atmega32c1
Description
Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA32C1.pdf
(366 pages)
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15.2.4
7647A–AVR–02/08
SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 15-2.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
functionality is summarized below:
Table 15-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
Bit
Read/Write
Initial Value
CPOL
CPHA
CPOL Functionality
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 15-3
SPE
R/W
6
0
and
DORD
R/W
5
0
Figure 15-4
Figure 15-3
Leading Edge
Leading Edge
Sample
MSTR
Falling
Rising
R/W
Setup
4
0
for an example. The CPOL functionality is sum-
and
CPOL
R/W
3
0
Figure 15-4
ATmega32/64/M1/C1
CPHA
R/W
2
0
for an example. The CPOL
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
163
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