atmega32c1 ATMEL Corporation, atmega32c1 Datasheet - Page 22
atmega32c1
Manufacturer Part Number
atmega32c1
Description
Atmega32m1 Automotive 8-bit Avr Microcontroller With 32k/64k Bytes In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA32C1.pdf
(366 pages)
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4.3
4.3.1
22
EEPROM Data Memory
ATmega32/64/M1/C1
EEPROM Read/Write Access
Figure 3. On-chip Data SRAM Access Cycles
The ATmega32/64/M1/C1 contains 1024/2048 bytes of data EEPROM memory. It is organized
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
Downloading” on page 305
mands” on page 293
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some
Address
clk
Data
Data
WR
CPU
RD
respectively.
, and
Compute Address
“Parallel Programming Parameters, Pin Mapping, and Com-
T1
Memory Access Instruction
27.for details on how to avoid problems in these
Table
Address valid
T2
4-2. A self-timing function, however,
Next Instruction
T3
7647A–AVR–02/08
“Serial
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