dspic33fj128gp706at-i-pt Microchip Technology Inc., dspic33fj128gp706at-i-pt Datasheet - Page 320

• Manufacturer Part Number: dspic33fj128gp706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJXXXGPX06A/X08A/X10A
ECAN Registers
Electrical Characteristics................................................... 263
Enhanced CAN Module..................................................... 197
Equations
Errata .................................................................................. 16
F
Flash Program Memory....................................................... 75
Flexible Configuration ....................................................... 243
FSCM
I
I/O Ports ............................................................................ 161
I
I
In-Circuit Debugger ........................................................... 250
In-Circuit Emulation........................................................... 243
In-Circuit Serial Programming (ICSP) ....................... 243, 250
Input Capture
Input Change Notification Module ..................................... 162
Instruction Addressing Modes............................................. 65
Instruction Set
Instruction-Based Power-Saving Modes ........................... 153
Internal RC Oscillator
Internet Address................................................................ 321
Interrupt Control and Status Registers................................ 91
Interrupt Setup Procedures ............................................... 131
DS70593A-page 318
2
2
C
C Module
ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 59
ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 59, 60
Frame Types ............................................................. 197
Modes of Operation .................................................. 199
Overview ................................................................... 197
Filter 15-8 Mask Selection Register (CiFMSKSEL2). 215
AC ............................................................................. 272
Device Operating Frequency .................................... 144
Control Registers ........................................................ 76
Operations .................................................................. 76
Programming Algorithm .............................................. 79
RTSP Operation.......................................................... 76
Table Instructions........................................................ 75
Delay for Crystal and PLL Clock Sources ................... 85
Device Resets ............................................................. 85
Parallel I/O (PIO)....................................................... 161
Write/Read Timing .................................................... 162
Operating Modes ...................................................... 183
Registers ................................................................... 183
I2C1 Register Map ...................................................... 51
I2C2 Register Map ...................................................... 51
Registers ................................................................... 172
File Register Instructions ............................................ 65
Fundamental Modes Supported.................................. 66
MAC Instructions......................................................... 66
MCU Instructions ........................................................ 65
Move and Accumulator Instructions ............................ 66
Other Instructions........................................................ 66
Overview ................................................................... 254
Summary................................................................... 251
Idle ............................................................................ 154
Sleep ......................................................................... 153
Use with WDT ........................................................... 249
IECx ............................................................................ 91
IFSx............................................................................. 91
INTCON1 .................................................................... 91
INTCON2 .................................................................... 91
IPCx ............................................................................ 91
Initialization ............................................................... 131
Preliminary
Interrupt Vector Table (IVT) ................................................ 87
Interrupts Coincident with Power Save Instructions ......... 154
J
JTAG Boundary Scan Interface ........................................ 243
M
Memory Organization ......................................................... 37
Microchip Internet Web Site.............................................. 321
Modes of Operation
Modulo Addressing ............................................................. 66
MPLAB ASM30 Assembler, Linker, Librarian ................... 260
MPLAB ICD 2 In-Circuit Debugger ................................... 261
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
MPLAB Integrated Development Environment Software.. 259
MPLAB PM3 Device Programmer .................................... 261
MPLAB REAL ICE In-Circuit Emulator System ................ 261
MPLINK Object Linker/MPLIB Object Librarian ................ 260
N
NVM Module
O
Open-Drain Configuration................................................. 162
Output Compare ............................................................... 173
P
Packaging ......................................................................... 303
Peripheral Module Disable (PMD) .................................... 154
PICSTART Plus Development Programmer..................... 262
Pinout I/O Descriptions (table)............................................ 19
PMD Module
POR and Long Oscillator Start-up Times ........................... 85
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Power-Saving Features .................................................... 153
Interrupt Disable ....................................................... 131
Interrupt Service Routine .......................................... 131
Trap Service Routine ................................................ 131
Disable...................................................................... 199
Initialization ............................................................... 199
Listen All Messages.................................................. 199
Listen Only................................................................ 199
Loopback .................................................................. 199
Normal Operation ..................................................... 199
Applicability................................................................. 68
Operation Example ..................................................... 67
Start and End Address ............................................... 67
W Address Register Selection .................................... 67
ulator......................................................................... 261
Register Map .............................................................. 64
Details....................................................................... 307
Marking ............................................................. 303, 304
Register Map .............................................................. 64
Register Map .............................................................. 62
Register Map .............................................................. 62
Register Map .............................................................. 63
Register Map .............................................................. 63
Register Map .............................................................. 63
Register Map .............................................................. 63
Register Map .............................................................. 64
© 2009 Microchip Technology Inc.