mb90f377pff-g Fujitsu Microelectronics, Inc., mb90f377pff-g Datasheet - Page 101
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mb90f377pff-g
Manufacturer Part Number
mb90f377pff-g
Description
16-bit Proprietary Microcontroller
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
1.MB90F377PFF-G.pdf
(140 pages)
- Current page: 101 of 140
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22. DTP/External interrupts
(1) Register configuration
DTP/Interrupt Source Register
DTP/Interrupt Enable Register
Request Level Setting Register (Upper)
Request Level Setting Register (Lower)
The DTP (Data Transfer Peripheral) /external interrupt circuit is activated by the signal supplied to a DTP/external
interrupt pin. The CPU accepts the signal using the same as procedure used for normal hardware interrupts
and generates external interrupts or activates the extended intelligent I/O service (EI
Features of DTP/External interrupt :
• Total 6 external interrupt channels
• Two request levels (“H” and “L”) are provided for the intelligent I/O service.
• Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests .
Address : 000027
Address : 000026
Address : 000029
Address : 000028
Initial value
Initial value
Initial value
Initial value
Read/write
Read/write
Read/write
Read/write
H
H
H
H
R/W
LB3
15
15
7
7
0
R/W
LA3
14
14
6
6
0
EN5
R/W
R/W
ER5
R/W
LB2
13
13
5
0
5
0
0
EN4
R/W
R/W
ER4
R/W
LA2
12
12
4
0
4
0
0
EN3
R/W
R/W
ER3
R/W
R/W
LB1
LB5
11
11
0
3
0
0
3
0
MB90370/375 Series
R/W
EN2
R/W
R/W
R/W
ER2
LA1
LA5
10
10
2
0
2
0
0
0
ER1
R/W
EN1
R/W
R/W
R/W
LB4
LB0
1
0
1
0
9
0
9
0
2
EN0
ER0
R/W
R/W
R/W
LA0
R/W
LA4
OS) .
0
0
0
0
8
0
8
0
Bit number
EIRR
Bit number
ENIR
Bit number
ELVRH
Bit number
ELVRL
101
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