mb90f377pff-g Fujitsu Microelectronics, Inc., mb90f377pff-g Datasheet - Page 96

• Manufacturer Part Number: mb90f377pff-g
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: Fujitsu Microelectronics, Inc.

96
MB90370/375 Series
19. Parity generator
(1) Register configuration of parity generator
Parity Generator Data Register
Parity Generator Control Status Register
The parity generator is a simple circuit that generates odd even parity based on the input data. It consists of a
parity generator data register (PGDR) , an odd even parity generation logic and a parity generator control status
register (PGCSR) .
An 8-bit data can be loaded into PGDR, then the parity generator will generate odd even parity based on the
input data. Either odd or even parity can be generated by setting the PGCSR.
For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “1”, otherwise the parity bit will be set to “0”.
For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will
be set to “0”, otherwise the parity bit will be set to “1”.
Table shows some examples of odd even parity generation.
Address : 000018
Address : 000019
0000 0000
0101 0101
1000 0000
1010 1011
Input data
Initial value
Initial value
Read/write
Read/write
B
B
B
B
H
H
PRTY
R/W
D7
15
X
R
7
X
R/W
D6
14
6
X
Parity bit (odd parity)
R/W
D5
13
X
5
1
1
0
0
R/W
D4
12
X
4
R/W
D3
11
X
3
R/W
D2
10
2
X
R/W
D1
1
X
9
Parity bit (even parity)
PSEL
R/W
R/W
D0
0
X
8
0
0
0
1
1
Bit number
PGDR
Bit number
PGCSR