c8051t623-g Silicon Laboratories, c8051t623-g Datasheet - Page 117

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c8051t623-g

Manufacturer Part Number
c8051t623-g
Description
Full Speed Usb Eprom Mcu Family
Manufacturer
Silicon Laboratories
Datasheet

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C8051T622/3 and C8051T326/7
USB Register Definition 18.5. CLKREC: Clock Recovery Control
USB Register Address = 0x0F
18.5. FIFO Management
256 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between
Endpoints0-2 as shown in Figure 18.3. FIFO space allocated for Endpoints1-2 is configurable as IN, OUT,
or both (Split Mode: half IN, half OUT).
124
Name
Reset
Bit
4:0 Reserved Reserved. Read = Variable. Must Write = 01111b.
Type
7
6
5
Bit
CRSSEN Clock Recovery Single Step.
CRLOW Low Speed Clock Recovery Mode.
Name
CRE
CRE
R/W
7
0
Clock Recovery Enable Bit.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
This bit forces the oscillator calibration into ‘single-step’ mode during clock
recovery.
0: Normal calibration mode.
1: Single step mode.
This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
CRSSEN
R/W
6
0
CRLOW
R/W
5
0
Reserved
R/W
Rev. 1.1
4
0
Function
Reserved
R/W
3
1
Reserved
R/W
2
1
Reserved
R/W
1
1
Reserved
R/W
0
1

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