c8051t623-g Silicon Laboratories, c8051t623-g Datasheet - Page 76

• Manufacturer Part Number: c8051t623-g
• Description: Full Speed Usb Eprom Mcu Family
• Manufacturer: Silicon Laboratories

SFR Definition 15.1. VDM0CN: V
SFR Address = 0xFF
15.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 6.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
15.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST pin is unaffected by this reset.
15.5. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “24.4. Watchdog Timer Mode” on
page 235; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
Name
Reset
Bit
5:0
Type
7
6
Bit
VDDSTAT
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 15.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source. See Table 6.4 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Unused. Read = Varies; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Varies
R
5
C8051T622/3 and C8051T326/7
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Varies
Rev. 1.1
DD
R
4
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
Varies
R
3
DD
Varies
DD
Monitor turn-on time.
R
2
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
Varies
R
1
Varies
R
0
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