mc9s12q128 Freescale Semiconductor, Inc, mc9s12q128 Datasheet - Page 388
mc9s12q128
Manufacturer Part Number
mc9s12q128
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12Q128.pdf
(644 pages)
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Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
13.3.2.5
Read: Anytime
Write: Anytime; writing accesses SCI status register 2; writing to any bits except TXDIR and BRK13
(SCISR2[1] & [2]) has no effect
388
Module Base + 0x_0005
Reset
TXDIR
Field
BK13
RAF
2
1
0
W
R
Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit
respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.
0 Break Character is 10 or 11 bit long
1 Break character is 13 or 14 bit long
Transmitter Pin Data Direction in Single-Wire Mode. — This bit determines whether the TXD pin is going to
be used as an input or output, in the Single-Wire mode of operation. This bit is only relevant in the Single-Wire
mode of operation.
0 TXD pin to be used as an input in Single-Wire mode
1 TXD pin to be used as an output in Single-Wire mode
Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start
bit search. RAF is cleared when the receiver detects an idle character.
0 No reception in progress
1 Reception in progress
SCI Status Register 2 (SCISR2)
0
0
7
= Unimplemented or Reserved
0
0
6
Figure 13-7. SCI Status Register 2 (SCISR2)
Table 13-6. SCISR2 Field Descriptions
0
0
5
MC9S12Q128
Rev 1.09
0
0
4
Description
0
0
3
BK13
0
2
Freescale Semiconductor
TXDIR
0
1
RAF
0
0
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