mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 99
mc56f8335
Manufacturer Part Number
mc56f8335
Description
16-bit Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC56F8335.pdf
(160 pages)
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5.6.30.6
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8
This bit controls whether the external IRQB interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
5.6.30.9
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
5.7 Resets
5.7.1
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except
the core IRQs with fixed priorities:
These interrupts are enabled at their fixed priority levels.
Freescale Semiconductor
Preliminary
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0 = IRQB interrupt is a low-level sensitive (default)
1 = IRQB interrupt is falling-edge sensitive.
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive.
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
Reset Handshake Timing
ITCN After Reset
IRQB State Pin (IRQB STATE)—Bit 3
IRQA State Pin (IRQA STATE)—Bit 2
IRQB Edge Pin (IRQB Edg)—Bit 1
IRQA Edge Pin (IRQA Edg)—Bit 0
56F8335 Technical Data, Rev. 5
Resets
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