r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 595

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
26.9
26.9.1
26.9.2
To use the I
26.9.1.1
26.9.2.1
26.9.2.2
26.9.2.3
After a master receive operation is completed, when a stop condition generation or a start condition
regeneration overlaps with the falling edge of the ninth clock cycle of SCL, an additional cycle is output after
the ninth clock cycle.
After a master receive operation is completed, confirm the falling edge of the ninth clock cycle of SCL and
generate a stop condition or regenerate a start condition.
Confirm the falling edge of the ninth clock cycle of SCL as follows: Confirm the SCLO bit in the ICCR2
register (SCL monitor flag) becomes 0 (SCL pin is low) after confirming the RDRF bit in the ICSR register
(receive data register full flag) becomes 1.
When writing 0 to the ICE bit or 1 to the IICRST bit during an I
ICCR2 register and the STOP bit in the ICSR register may become undefined.
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When this module occupies the bus in master transmit mode (bits MST and TRS in the ICCR1 register are 1).
When this module occupies the bus in master receive mode (the MST bit is 1 and the TRS bit is 0).
When this module transmits data in slave transmit mode (the MST bit is 0 and the TRS bit is 1).
When this module transmits an acknowledge in slave receive mode (bits MST and TRS are 0).
When the start condition (the SDA falling edge when SCL is high) is input, the BBSY bit becomes 1.
When the stop condition (the SDA rising edge when SCL is high) is input, the BBSY bit becomes 0.
When writing 1 to the BBSY bit, 0 to the SCP bit, and the start condition (the SDA falling edge when SCL is
high) is output while SCL and SDA are high in master transmit mode, the BBSY bit becomes 1.
When writing 0 to bits BBSY and SCP, the stop condition (the SDA rising edge when SCL is high) is output
while SDA is low, and this is the only module that holds SCL low in master transmit mode or master receive
mode, the BBSY bit becomes 0.
When writing 1 to the FS bit in the SAR register, the BBSY bit becomes 0.
When writing 1 to the IICRST bit, bits SDAO and SCLO in the ICCR2 register become 1.
When writing 1 to the IICRST bit in master transmit mode and slave transmit mode, the TDRE bit in the ICSR
register becomes 1.
While the control block of the I2C bus interface is reset by setting the IICRST bit to 1, writing to bits BBSY,
SCP, and SDAO is disabled. Write 0 to the IICRST bit before writing to the BBSY bit, SCP bit, or SDAO bit.
Even when writing 1 to the IICRST bit, the BBSY bit does not become 0. However, the stop condition (the
SDA rising edge when SCL is high) may be generated depending on the states of SCL and SDA and the
BBSY bit may become 0. There may also be a similar effect on other bits.
While the control block of the I2C bus interface is reset by setting the IICRST bit to 1, data transmission/
reception is stopped. However, the function to detect the start condition, stop condition, or arbitration lost
operates. The values in the ICCR1 register, ICCR2 register, or ICSR register may be updated depending on
the signals applied to pins SCL and SDA.
Notes on I
Master Receive Mode
The ICE Bit in the ICCR1 Register and the IICRST Bit in the ICCR2 Register
2
C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I
Countermeasure
Conditions When Bits Become Undefined
Countermeasures
Additional Descriptions Regarding the IICRST Bit
2
C bus Interface
2
C bus interface operation, the BBSY bit in the
2
C bus interface function selected).
26. I
Page 563 of 740
2
C bus Interface