cop87l84bc National Semiconductor Corporation, cop87l84bc Datasheet - Page 45

• Manufacturer Part Number: cop87l84bc
• Description: 8-bit Cmos Otp Microcontrollers With 16k Memory, Comparators, And Can Interface
• Manufacturer: National Semiconductor Corporation

Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
00 to 2F
30 to 7F
80 to 9F
A0
A1
A2
A3 to AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0 to C7
C8
C9
CA
CB to CF
D0
D1
D2
D3
D4
D5
D6
D7 to DB
DC
DD to DF
E0 to E5
E6
E7
E8
E9
Address
On-Chip RAM bytes (48 bytes)
Unused RAM Address Space (Reads As All
Ones)
Unused RAM Address Space (Reads
Undefined Data)
PSCAL, PWM timer Prescaler Register
RLON, PWM timer On-Time Register
PWMCON, PWM Control Register
Reserved
TXD1, Transmit 1 Data
TXD2, Transmit 2 Data
TDLC, Transmit Data Length Code and
Identifier Low
TID, Transmit Identifier High
RXD1, Receive Data 1
RXD2, Receive Data 2
RIDL, Receive Data Length Code
RID, Receive Identify High
CSCAL, CAN Prescaler
CTIM, Bus Timing Register
CBUS, Bus Control Register
TCNTL, Transmit/Receive Control Register
RTSTAT Receive/Transmit Status Register
TEC, Transmit Error Count Register
REC, Receive Error Count Register
Reserved
Reserved
WKEDG, MIWU Edge Select Register
WKEN, MIWU Enable Register
WKPND, MIWU Pending Register
Reserved
PORTLD, Port L Data Register
PORTLC, Port L Configuration Register
PORTLP, Port L Input Pins (Read Only)
CMPSL, Comparator control register
PORTGD, Port G Data Register
PORTGC, Port G Configuration Register
PORTGP, Port G Input Pins (Read Only)
Reserved
PORTD, Port D output register
Reserved for Port D
Reserved
T1RBLO, Timer T1 Autoload Register Lower
Byte
T1RBHI, Timer T1 Autoload Register Upper
Byte
ICNTRL, Interrupt Control Register
SIOR, MICROWIRE/PLUS Shift Register
Contents
45
Note 15: Reading memory locations 30–7F Hex will return all ones. Reading
other unused memory locations will return undefined data.
Note 16: In devices with more than 128 bytes of RAM, location 0FF is used
as the Segment register to switch between different Segments of RAM
memory. In this device location 0FF can be used as a general purpose, on-
chip RAM mapped register. However, the user is advised that caution should
be taken in porting software utilizing this memory location to a chip with more
than 128 bytes of RAM.
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post Increment or
decrement of pointer)
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
ter after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the oper-
and.
Short Immediate
This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumuiator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
EA
EB
EC
ED
EE
EF
F0 to FB
FC
FD
FE
FF
Address
TMR1LO, Timer T1 Lower Byte
TMR1HI, Timer T1 Upper Byte
T1RALO, Timer T1 Autoload Register Lower
Byte
T1RAHI, Timer T1 Autoload Register T1RA
Upper Byte
CNTRL, Control Register
PSW, Processor Status Word Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved (Note 16)
Contents
www.national.com