scf5250 Freescale Semiconductor, Inc, scf5250 Datasheet - Page 14

• Manufacturer Part Number: scf5250
• Description: Scf5250 Integrated Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
4.5
There are three chip select outputs on the SCF5250 device. CS0/CS4 and CS1/QSPI_CS3/GPIO28 and
CS2 which is associated with the IDE interface read and write strobes - IDE-DIOR and IDE-DIOW.
CS0 and CS4 are multiplexed. The SCF5250 has the option to boot from an internal Boot Rom.
The function of the CS0/CS4 pin is determined by the boot mode. When the device is booted from internal
ROM, the internal ROM is accessed with CS0 (required for boot) and the CS0/CS4 pin is driven by CS4.
When the device is booted from external ROM / Flash, the CS0/CS4 pin is driven by CS0 and the internal
ROM is disabled.
The active low chip selects can be used to access asynchronous memories. The interface is glueless.
4.6
The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus
peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The
peripheral can insert wait states by pulling IDE-IORDY/GPIO33.
CS2 is associated with the IDE-DIOR and IDE-DIOW.
4.7
As the SCF5250 has a complicated slave bus, which allows SDRAM, asynchronous memories, and ISA
peripherals on the bus, it may become necessary to introduce a buffer on the bus in certain applications.
The SCF5250 has a glueless interface to steer these bus buffers with two bus buffer output signals
BUFENB1/GPIO29 and BUFENB2/GPIO30.
4.8
There are two I
The I
peripherals with an I
14
2
C module acts as a two-wire, bidirectional serial interface between the SCF5250 processor and
Synchronous DRAM UDQM and LQDM
Synchronous DRAM Clock Enable
Synchronous DRAM Chip Enable
Chip Selects
ISA bus
Bus Buffer Signals
I
2
Synchronous DRAM clock
C Module Signals
2
C interfaces on this device.
SDRAM Signal
signals
2
C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Table 4. SDRAM Controller Signals (continued)
The SD_CS0/GPIO60 active-low output signal is used during
synchronous mode to route directly to the chip select of a SDRAM
device.
The DRAM byte enables UDMQ and LDQM are driven by the
SDUDQM/GPO53 and SDLDQM/GPO52 byte enable outputs.
The DRAM clock is driven by the BCLK/GPIO40 signal
The BCLKE active high output signal is used during synchronous mode
to route directly to the SCKE signal of external SDRAMs. This signal
provides the clock enable to the SDRAM.
Description
Freescale Semiconductor