m30800sagp Renesas Electronics Corporation., m30800sagp Datasheet - Page 13

• Manufacturer Part Number: m30800sagp
• Description: Single-chip 16/32-bit Cmos Microcomputer
• Manufacturer: Renesas Electronics Corporation.

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2.1 General Registers
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2.1.1 Data Registers (R0, R1, R2 and R3)
2.1.2 Address Registers (A0 and A1)
2.1.3 Static Base Register (SB)
2.1.4 Frame Base Register (FB)
2.1.5 Program Counter (PC)
2.1.6 Interrupt Table Register (INTB)
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
2.1.8 Flag Register (FLG)
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R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith-
metic and logic operations.
SB is a 24-bit register for SB-relative addressing.
FB is a 24-bit register for FB-relative addressing.
PC, 24 bits wide, indicates the address of an instruction to be executed.
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
FLG is a 16-bit register indicating a CPU state.
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2.1.8.1 Carry Flag (C)
2.1.8.2 Debug Flag (D)
2.1.8.3 Zero Flag (Z)
2.1.8.4 Sign Flag (S)
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The C flag indicates whether carry or borrow has occurred after executing an instruction.
The D flag is for debug only. Set to "0".
The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".
The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
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Page 13
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2. Central Processing Unit (CPU)