mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet - Page 18

• Manufacturer Part Number: mb91307r
• Description: 32-bit Microcontroller Cmos Fr60 Mb91307 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

18
MB91307 Series
• Terminal and timing control register (TCR) (0x00000683)
• RD/WR → CS hold extension cycle
• Signed DIVIDE statement (DIVOS)
The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit
manipulation instruction.
If you intend to disable sharing of the bus by writing “0” to Bit 7 (BREN bit) of TCR when the bit is “1”, be sure
to follow the procedure below. If the procedure is not followed, the device may hang up.
1. Write “0” to Bit 2 (BRQE bit) of the port 8 function register (PFR8).
2. Write “0” to Bit 7 (BREN bit) of TCR.
Assume that use of the RD/WR
area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are
0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and
settings are specified in a specific combination.
The hold extension cycle will not be inserted when the following conditions are met:
• Use of the RD/WR
• A normal memory/IO access type is set for the area.
• Disuse of the address
• A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle.
• If an access is made to write data larger than the bus width to the relevant area under the above conditions,
To use this function, make either of the following settings:
• Specify the use of the address
• Specify 0 cycle for the write recovery cycle.
When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access
is done, a correct calculation result might not be obtained.
This is generated under the following conditions.
• When the instruction performs memory accesses just before a DIVOS instruction.
(Bit 0 [W00 bit] of AWR is 1.)
(Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.)
Note: The MB91307 series allows only this type to be set.
(Bit 2 [W02 bit] of AWR is 0.)
(Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.)
(Example: First word writing to an external bus 16-bit area)
the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of
the data. Therefore, the hold time becomes insufficient.
Note : This problem does not occur in the read cycle.
(Set 1 for Bit 2 [W02 bit] of AWR.)
(Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.)
Note : Instructions that performs relevant memory accesses (a total of 58 instructions)
ST Ri, @- R15
STB Ri, @Rj
STB Ri, @ (R14, disp8)
LDUH @ (R13, Rj), Ri
DMOVH @dir9, R13
→
CS hold extension cycle is specified.
→
CS delay cycle is specified.
→
→
ST Rs, @- R15
STB Ri, @ (R13, Rj)
LDUB @Rj, Ri
LDUB @ (R13, Rj), Ri
DMOVB @dir8, R13
CS hold extension cycle is specified (Bit 0 of AWR is 1) for an
CS delay cycle.
ST PS, @- R15
DMOVB R13, @dir8
LD @ (R13, Rj), Ri
DMOV @dir10, R13
LD @ (R14, disp10), Ri