mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet - Page 20

• Manufacturer Part Number: mb91307r
• Description: 32-bit Microcontroller Cmos Fr60 Mb91307 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

20
MB91307 Series
• RMW instructions using R15
• Executing instructions on RAM
• Notes on the PS register
• Notes on I-bus Memory
If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and,
as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following
instructions:
* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the
Avoid this notes as follows:
• When programming any of the above 10 instructions by an assembler, specify a general-purpose register in
• If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.
place of R15.
0005 FFFF
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
AND
OR
EOR
XCHB
state of the S flag of the PS register.
same value as that in (1) above.
updated to the same values as those in (1) above.
R15,@Rj
R15,@Rj
@Rj,R15
R15,@Rj
H
. (Instruction code prohibited area)
ANDH
ORH
EORH
R15,@Rj
R15,@Rj
R15,@Rj
ANDB
ORB
EORB
R15,@Rj
R15,@Rj
R15,@Rj
H
to