mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet - Page 22

• Manufacturer Part Number: mb91307r
• Description: 32-bit Microcontroller Cmos Fr60 Mb91307 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

22
MB91307 Series
• Alignment error (emulator debugger)
• Operand break
Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed
between an instruction to read a branch destination address from memory and a branch instruction. Under these
conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur
originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown
break factor or a CPU error break is output.
Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.
This problem occurs if the following three types of instructions are executed successively:
Avoid this notes as follows:
Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed
between an instruction to read a branch destination address from memory and a branch instruction. Under these
conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur
originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown
break factor or a CPU error break is output.
Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.
Avoid this problem as follows:
• To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger
• To perform the instruction break correctly, set the break point in an address other than the branch destination
A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
function setup.
address.
(1) LD or DMOV instructions causing a wait (reading a branch destination address)
(2) Instructions causing a wait (reading F-bus RAM or external memory)
(3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D
Example:
LD
LD
LD
LD
DMOV @dir10,R13
@Rj,Ri
@(R13,Rj)Ri
@(R14,disp10),Ri LDUH @(R14,disp9),Ri LDUB @(R14,disp8),Ri
@R15+,Ri
LD@R1,R0
LD@R2,R3
CALL @R0
;read F-bus RAM
;read F-bus RAM
LDUH @Rj,RI
LDUH @(R13,Rj),Ri
LD @R15+,Rs
DMOVH @dir9,R13
LDUB @(R13,Rj),Ri
LD @R15+,PS
DMOVB @dir8,R13