w78l812a Winbond Electronics Corp America, w78l812a Datasheet
w78l812a
Available stocks
Related parts for w78l812a
w78l812a Summary of contents
Page 1
... Watchdog Timer Control Register ...............................................................................12 5.7 Clock ............................................................................................................................. 13 5.8 Power Management...................................................................................................... 13 5.8.1 Idle Mode.....................................................................................................................13 5.8.2 Power-down Mode.......................................................................................................14 5.9 AUXR - Auxiliary Register............................................................................................. 14 5.10 Reduce EMI Emission .................................................................................................. 14 5.11 Reset............................................................................................................................. 14 6. ON-CHIP ROM CHARACTERISTICS ...................................................................................... 15 6.1 Read Operation ............................................................................................................ 15 6.2 Output Disable Condition.............................................................................................. 15 6.3 Program Operation ....................................................................................................... 15 6.4 Program Verify Operation ............................................................................................. 15 6.5 Erase Operation............................................................................................................ 15 W78LE812/W78L812A 8-BIT MICROCONTROLLER Publication Release Date: November 6, 2006 - 1 - Revision A9 ...
Page 2
... Data Read Cycle........................................................................................................... 24 10.3 Data Write Cycle ........................................................................................................... 25 10.4 Port Access Cycle......................................................................................................... 25 10.5 Program Operation ....................................................................................................... 26 11. TYPICAL APPLICATION CIRCUITS ........................................................................................ 27 11.1 Expanded External Program Memory and Crystal ....................................................... 27 11.2 Expanded External Data Memory and Oscillator ......................................................... 28 12. PACKAGE DIMENSIONS ......................................................................................................... 29 12.1 40-pin DIP ..................................................................................................................... 29 12.2 44-pin PLCC ................................................................................................................. 29 12.3 44-pin PQFP ................................................................................................................. 30 12.4 48-pin LQFP.................................................................................................................. 30 13. REVISION HISTORY ................................................................................................................ 31 W78LE812/W78L812A - 2 - ...
Page 3
... Wake-up via external interrup EMI reduction mode Built-in power management Code protection mechanism Packages: − Lead Free (RoHS) DIP 40: − Lead Free (RoHS) PLCC 44: W78L812A24PL − Lead Free (RoHS) PQFP 44: W78L812A24FL − Lead Free (RoHS) LQFP 48: W78L812A24LL W78LE812/W78L812A Flash EPROM ce pace ...
Page 4
... ALE A13CTRL,TXD, P3.1 32 A14CTRL,INT0, P3.2 PSEN,P4.6 31 P2.7, A15 OECTRL,INT1, P3.3 30 P2.6, A14 T0, P3.4 29 T1, P3.5 P2.5, A13 W78LE812/W78L812A 44-Pin PQFP ...
Page 5
... W78LE812/W78L812A Publication Release Date: November 6, 2006 - 5 - Revision A9 ...
Page 6
... T0(P3.4): Timer 0 External Input T1(P3.5): Timer 1 External Input WR (P3.6): External Data Memory Write Strobe RD (P3.7): External Data Memory Read Strobe PORT 4: A 5-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are − available on 44-pin PLCC/QFP package. P4.6 is the alternative function corresponding to P4.0 P4.6 PSEN . W78LE812/W78L812A DESCRIPTIONS − P1.7): External interrupt ...
Page 7
... Clock-out Frequency = Oscillator Frequency / [4 × (65536-RCAP2H, RCAP2L)] OSC TR2 (T2CON.2) T2EX (P1.1) EXEN2 (T2CON.3) Timer 2 Clock-Out Mode 5.2 Timer 2 Mode Control Bit Mnemonic: T2MOD T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. W78LE812/W78L812A 1/2 TL2 TH2 RCAP2L RCAP2H ...
Page 8
... P4.6 that serve as general purpose I/O pins. To enable I/O port P4.6, the bit EP6 in the POR register must be set. During reset, the, PSEN perform as in the standard 80C32. The alternate functions P4.6 must be enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. 5.4.1 Port 4 Bit P4.6 Mnemonic: P4 W78LE812/W78L812A HD7 HD6 Address: 86H 6 ...
Page 9
... EX9: Enable external interrupt 9 EX8: Enable external interrupt 8 EX7: Enable external interrupt 7 EX6: Enable external interrupt 6 EX5: Enable external interrupt 5 EX4: Enable external interrupt 4 EX3: Enable external interrupt 3 EX2: Enable external interrupt 2 W78LE812/W78L812A INT and INT1 ; Timer 0,1 and 2; Serial Port; INT2 ...
Page 10
... PT1 = 1 sets it to higher priority level. PT0 = 1 sets it to higher priority level PX7 PX6 PX5 Mnemonic: IP1 Address: F8h IL7 IL6 IL5 Mnemonic: IX Address: E9H - 10 - W78LE812/W78L812A PX1 PT0 PX0 PX4 PX3 PX2 IL4 IL3 IL2 ...
Page 11
... External Interrupt 0 Serial Port External Interrupt 5 Timer 0 Overflow External Interrupt 6 External Interrupt 1 External Interrupt 2 External Interrupt 7 Timer 1 Overflow Timer 2 Overflow External Interrupt 3 External Interrupt 8 External Interrupt 4 External Interrupt 9 W78LE812/W78L812A IQ7 IQ6 IQ5 Address: C0H FLAG PRIORITY LEVEL IE0 (Highest ...
Page 12
... After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset WIDL - - Mnemonic: WDTC Address: 8FH 1 14 × × × 2 PRESCALER 1000 W78LE812/W78L812A PS2 PS1 PS0 PRESCALER SELECT 128 256 × mS ...
Page 13
... The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. W78LE812/W78L812A ENW EXTERNAL ...
Page 14
... During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. W78LE812/W78L812A 6 5 ...
Page 15
... This operation allows parallel erasing or programming of multiple chips with different data. When P3 P3 erasing or programming of non-targeted chips is inhibited. So, except IH IH for the P3.6 and P3.7 pins, the individual chips may have common inputs. W78LE812/W78L812A ( EA ). Moreover, the A15 − A0 (P2.7 − P2.0, P1.7 − P1.0) PP (12.5V) level, CE set to low, and OE set to high. CP Publication Release Date: November 6, 2006 - 15 - ...
Page 16
... The register can only be accessed from the on-chip ROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by address #0FFFFh. W78LE812/W78L812A P3.2 P3.3 P3.6 P3 ...
Page 17
... MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. W78LE812/W78L812A Security Bits B0 Special Setting Register ...
Page 18
... Vss Programming Configuration 7. ABSOLUTE MAXIMUM RATINGS PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. W78LE812/W78L812A +5V PGM DATA ...
Page 19
... P0, EA Logic 1-to-0 Transition Current P1, P2, P3, P4 Input Low Voltage P1, P2, P3, P4 Input Low Voltage [*3] RST Input Low Voltage [*3] XTAL1 Input High Voltage P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage [*4] XTAL1 W78LE812/W78L812A SPECIFICATION SYM. MIN. MAX. V 2.4 5 IDLE - 1 ...
Page 20
... I SK1 1.8 5 SK2 4 SK3 2 OH1 1 OH2 1.4 - -120 -250 I SR1 -20 -40 -10 -14 I SR2 -1.9 -3 W78LE812/W78L812A TEST CONDITIONS UNIT 4.5V 2.4V 4.5V 2.4V 4.5V 4.5V 0.45V 2.4V ...
Page 21
... XTAL1 PARAMETER Operating Speed Clock Period Clock High Clock Low Notes: 1. The clock may be stopped indefinitely in either state. 2. The T specification is used as a reference in other specifications There are no duty cycle requirements on the XTAL1 input. W78LE812/W78L812A OP, CP SYMBOL MIN. ...
Page 22
... Data Write Cycle PARAMETER ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width Note: " Δ " (due to buffer driving delay and wire loading nS. W78LE812/W78L812A SYMBOL MIN. TYP -Δ AAS CP ...
Page 23
... OECTRL Setup Time OECTRL Hold Time OE Setup Time OE High to Output Float Data Valid from OE Note: Flash data can be accessed only in flash mode. The RST pin must pull in V and the PSEN pin must pull W78LE812/W78L812A SYMBOL MIN PDS ...
Page 24
... TIMING WAVEFORMS 10.1 Program Fetch Cycle S1 S2 XTAL1 ALE PSEN T AAS PORT 2 T AAH PORT 0 A0-A7 Code 10.2 Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT 0 RD W78LE812/W78L812A ALW T APL T PSW T PDA T T PDH, PDZ A0-A7 Code Data A8-A15 ...
Page 25
... Data Write Cycle S4 S5 XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR 10.4 Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE W78LE812/W78L812A A8-A15 DATA OUT T T DWD DAD T T DWR DAW PDH Publication Release Date: November 6, 2006 - ...
Page 26
... P3 (CE P3.3 IH (OECTRL P3 (OE (A7... A0 Vcp Vpp VPS Program Program Verify Address Stable T PWP OCS T OCH T OES T DH Data In D OUT T OEV - 26 - W78LE812/W78L812A Read Verify Address Valid T DFP Data Out ...
Page 27
... TYPICAL APPLICATION CIRCUITS 11.1 Expanded External Program Memory and Crystal CRYSTAL 16 MHz 20 MHz Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. W78LE812/W78L812A Figure 30P 30P 15P 15P Publication Release Date: November 6, 2006 - Revision A9 ...
Page 28
... EA 19 XTAL1 O SCILLA XTAL2 8 RST INT0 12 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7 W 78LE812/W 78L812A W78LE812/W78L812A AD0 AD0 3 P0 AD1 AD1 AD2 AD2 P0 AD3 AD3 8 P0 AD4 A4 P0 ...
Page 29
... 12.2 44-pin PLCC θ Seating Plane W78LE812/W78L812A Base Plane A 1 Seating Plane Publication Release Date: November 6, 2006 - 29 - Dimension in inch Dimension in mm Symbol Min ...
Page 30
... PQFP See Detail F y Seating Plane 12.4 48-pin LQFP See Detail F Seating Plane W78LE812/W78L812A θ Detail Detail F ...
Page 31
... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W78LE812/W78L812A PAGE REASONS FOR CHANGE - 26 ...