km416s8030bn Samsung Semiconductor, Inc., km416s8030bn Datasheet - Page 3

• Manufacturer Part Number: km416s8030bn
• Description: 128mb Sdram Shrink Tsop 16bit Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM416S8030BN
2M x 16Bit x 4 Banks Synchronous DRAM in New Shrink-TSOP(sTSOP)
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
clock.
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
* Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
shrink-TSOP
CAS
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 2,097,152 words by 16
bits, fabricated with SAMSUNG s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Programming Register
WE
KM416S8030BN-G/FH 100MHz(CL=2)
KM416S8030BN-G/FL
The KM416S8030B is 134,217,728 bits synchronous high data
Data Input Register
Column Decoder
2M x 16
2M x 16
2M x 16
2M x 16
Part No.
LDQM
LWCBR
UDQM
100MHz(CL=3)
Max Freq.
Rev. 0.1 Aug. 1999
CMOS SDRAM
LDQM
Preliminary
Interface Package
LVTTL
LWE
LDQM
DQi
sTSOP(II)
54pin