x5083s8izt2 Intersil Corporation, x5083s8izt2 Datasheet - Page 6
x5083s8izt2
Manufacturer Part Number
x5083s8izt2
Description
Cpu Supervisor With 8kbit Spi Eeprom
Manufacturer
Intersil Corporation
Datasheet
1.X5083S8IZT2.pdf
(21 pages)
- Current page: 6 of 21
- Download datasheet (321Kb)
SCK
SCK
WP
WP
CS
CS
SI
SI
V
Adj.
TRIP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
WREN
WREN
06h
06h
V
P
6
FIGURE 1. SET V
FIGURE 2. RESET V
Adjust
Run
FIGURE 3. SAMPLE V
TRIP
0 1 2 3 4 5 6 7 8 9 10
0 1 2 3 4 5 6 7 8 9 10
LEVEL SEQUENCE (V
TRIP
LEVEL SEQUENCE (V
V
V
Write
02h
P
P
Write
02h
1
2
3
4
= 15-18V
= 15-18V
X5083
X5083
TRIP
RESET CIRCUIT
8
7
6
5
CC
= DESIRED V
CC
> 3V. WP = 15-18V)
Address
16 Bits
16 Bits
0001h
Address
0003h
20 21 22 23
20 21 22 23
4.7K
TRIP
RESET
VALUE)
Data
00h
Data
SCK
SI
SO
CS
00h
µC
June 15, 2006
FN8127.3
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