lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 11

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Detailed Signal Definitions
is active, holding this pin LOW will hold the write address in its zero position continuously. This control
takes effect only when WEN is LOW.
RADDRSEL - Read Address Select
RADDRSEL selects the source of the read address. This pin and control MARKSEL select whether
RSET forces the read address to the RADDR configuration register (RADDRSEL = 0) or to ADDR[23:0]
(RADDRSEL = 1). This control takes effect only when REN is LOW.
WSET - Write Pointer Set
This control is active only when WCLR is HIGH. Bringing WSET LOW will cause the next rising edge
of WCLK to bring the current value on D[11:0] into memory at the address specified by WADDR, or at
the address present on ADDR[23:0]. Whenever WSET and WCLR are HIGH, the next rising edge of
WCLK will bring the current D[11:0] data value into the next-higher address in sequence. WSET may be
programmed to be either edge-triggered, in which case it affects the write pointer for only one clock cycle
following a falling edge, after which incrementing resumes, or level-triggered, in which case it affects the
write pointer until it is brought HIGH. For continuous random access write operation, holding WSET LOW
and programming it to be level-triggered will provide the needed continuous write pointer override. This
control takes effect only when WEN is LOW.
WADDRSEL - Write Pointer Set
WADDRSEL selects the source of the write address. WADDRSEL determines whether WSET forces
the write address pointer to the WADDR configuration register (WADDRSEL = 0) or to ADDR[23:0]
(WADDRSEL = 1). This control takes effect only when WEN is LOW.
MARK - Write Address Pointer Mark
Bringing this bit LOW will cause an internal register to store a copy the current value of the write address
pointer, for subsequent use in synchronizing the corresponding read address pointer to the same location.
Unlike WCLR and WSET, this control does not affect the write pointer value itself. The system must use
MARK instead of WCLR if the entire memory core can be filled between sequential falling edges of the
sync reference signal. In contrast, the system must use WCLR or WSET to establish a definite relationship
between the internal address and the data stream, as in random access read mode.
RSET - Read Address Pointer Set
If REN is LOW, bringing RSET LOW will force the read address to the most recently marked value
(MARK_SEL LOW), to RADDR (MARKSEL HIGH and RADRSEL LOW), or to ADDR[23:0] (MARK_SEL
is HIGH and RADRSEL is HIGH). This pin may be programmed to be either falling edge or level sensitive
active.
RCLR - Read Address Pointer Clear
Bringing RCLR LOW causes the next rising edge of RCLK to force the read address pointer to zero.
This pin may be programmed to be active on its falling edge or in its LOW state. It can reset the read
pointer only when REN is LOW.
WEN - Write Enable
If WEN is LOW, data on D11-0 is written to the device on the rising edge of WCLK. When WEN is HIGH,
the device ignores data on D and holds the write pointer. The user must anticipate the use of WEN by one
cycle. Therefore when desiring not to write a sample, WEN must be brought high the cycle before.
WIEN - Memory Write Enable (Write Masking)
WIEN is used to enable/disable writing into the memory core. A LOW on WIEN enables writing, while a
HIGH on WIEN disables writing. The internal write address pointer is incremented by WEN regardless of
the WIEN level. If disabling of WIEN is never desired, tie WIEN LOW.
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24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324