lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 7

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Programming
the LF3324
Serial MPU
Interface
LOGIC Devices Incorporated
Device Configuration
The LF3324 has two MPU interfaces. The first is a standard two wire serial interface following the I
protocol. The second is a parallel interface allowing the user to write a byte of data at a time to the
configuration registers. When the user wishes to use the serial interface, the PROGRAM pin must be set
LOW, while a HIGH selects the parallel interface. To provide users with more flexibility, the control registers
have been combined with a “working latch” . Ultimately, the register-latch combination allows users to
update the configuration registers during chip operation, and then to transfer the register contents to all
working latches simultaneously using the LOAD signal. When high, the LOAD signal allows the LF3324
to be pre-programmed during operation, and once brought low after programming updates the working
latches allowing the new changes to take effect. LOAD can also be maintained low to allow changes to the
configuration registers to be immediately reflected in the working latches.
When the PROGRAM pin is LOW, the serial interface is active. Up to 8 LF3324 devices can be connected
to and programmed by the serial interface. The two wire interface is composed of an SCL clock pin and a
bi-directional SDA data pin. When inactive, SDA and SCL are forced HIGH by external pull up resistors.
Data transmission is achieved over the SDA pin and must remain constant during the logical HIGH portion
of the SCL clock pulse. The level of SDA, while SCL is HIGH, is interpreted as the appropriate bit value as
will be shown later. Changing the data on SDA must only occur when SCL is low, because any changes
to SDA while SCL is HIGH is interpreted as a start or stop request, which are shown in Figure 7 with an
example data transfer in Figure 8.
The first operation to begin programming the LF3324 through the serial interface, is to send a start signal.
When the interface is inactive, a HIGH to LOW transition must be sent on SDA while SCL is HIGH, notifying
all connected devices (slaves) to expect a data transmission. When transferring data, the MSB of the eight
bit sequence is the first bit to be transmitted to or from the master or slave. The first byte of data to be
transmitted on SDA must consist of the 7-bit base address of the slave, along with an 8th READ/WRITE bit
as the LSB, which describes the direction of the data transmission. The slave whose 7-bit CHIP_ADDR6-0,
matches the 7-bit base address sent on SDA, will send an acknowledgement back to the master by bringing
SDA LOW on the 9th SCL pulse. NOTE: In order to differentiate the two internal die, die 0’s CHIP_ADDR(0)
is tied LOW and die 1’s CHIP_ADDR(0) is tied HIGH.
During a write operation, if the slave does not send an acknowledgment back to the master device, SDA is
left high which forces the master to generate a stop signal. In contrast, during a read operation, if there is no
acknowledgement back from the master device, the LF3324 interprets this as if it were the end of the data
transmission, and leaves SDA high, allowing the master to generate its stop signal.
Figure 5. I
SDA
SCL
2
C Start and Stop Signals
Start Signal
7
SDA
SCL
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Stop Signal
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324
2
C