lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 18

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Definitions
Register 9[2:0] = FLAG_SET[2:0] - sets fractional “fullness” and “emptiness” thresholds in
memory core.
Partially Full flag goes HIGH when the memory is more than “TH” full. Partially Empty flag goes
HIGH when the memory is less than or equal to “TL” full.
000
001
010
011
100
101
110
111
Register A[6] = WSET_catch
0
1
Register A[5:0] Control action.
Register B[7:4]=
-------
Rb[5]
Rb[4]
Rb[3]
Rb[2]
Rb[1]
Rb[0]
if 0:
if 1:
TH = 79/81 (default)
TH = 78/81
TH = 77/81
TH = 76/81
TH = 75/81
TH = 74/81
TH = 73/81
TH = 72/81
Setting Write Pointer does not “MARK” its new value (default)
Setting Write Pointer auto-MARKS its new value
RSET_b_sel
RCLR_b_sel
WADDRSEL_b_sel
RADDRSEL_b_sel
WSET_b_sel
WCLR_b_sel
Each falling edge on the corresponding control pin overrides a
memory address counter for exactly one clock cycle, after which
normal memory address incrementing immediately resumes. (default)
The corresponding pin continuously overrides the memory address
counter as long as it is held LOW. Memory address incrementing
resumes when the pin is returned HIGH.
Reserved
18
TL = 1/81 (default)
TL = 2/81
TL = 3/81
TL = 4/81
TL = 5/81
TL = 6/81
TL = 7/81
TL = 8/81
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324