le25lb643 Sanyo Semiconductor Corporation, le25lb643 Datasheet
le25lb643
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le25lb643 Summary of contents
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... LE25LB643 Overview The LE25LB643 is a 64Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation and high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. The interface is compatible with SPI bus protocol, therefore best suited for applications that require small-scale rewritable nonvolatile parameter memory ...
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... Package Dimensions unit : mm (typ) 3 032D [LE25LB643M] 5 (0.65) 1.27 0.35 0.15 SANYO : MFP8(225mil) Packages MFP8 (225mil) MSOP8 (150mil) Pin Assignment Block Diagram ADDRESS BUFFERS & LATCHES LE25LB643 unit : mm (typ) 3245B [LE25LB643TT (0.53) : LE25LB643M : LE25LB643TT Pin Descriptions PIN.1 PIN.2 PIN ...
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... Input pin capacitance Note : These parameters are sampled and not 100% tested. AC Electrical Characteristics Input pulse level Input pulse rise/fall time Output detection voltage Output load LE25LB643 Conditions Conditions Conditions HOLD = 0.1V DD /0. Open Operating frequency = 5MHz 3. 0. HOLD = ...
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... WP hold time t WPH HOLD setup time t HS HOLD hold time t HH HOLD output low impedance time t HLz HOLD output high impedance time t HHz Write cycle time t WC SCK output low impedance time t CLZ LE25LB643 Conditions min ...
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... SCK DATA VALID High Impedance SO (SPI Mode CLS t CSS SCK DATA VALID High Impedance SO LE25LB643 2nd bus 3rd bus 4th bus cycle cycle cycle DATA A15-A8 A7- A15-A8 A7-A0 t CLHI t CLLO High Impedance t CLLO t CLHI t DH High Impedance ...
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... Figure 3 Serial Output Timing (SPI Mode 0) CS SCK t CLZ (SPI Mode 3) CS SCK t CLZ LE25LB643 t HO DATA VALID t HO DATA VALID t CHZ t CHZ No.NA1342-6/14 ...
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... Addresses A15 - A13 are “don’t care.” • In synchronization with the rising edges clock signals, the command is identified and the addresses are taken in through SI. • In synchronization with the falling edges of 23 clock signal or later, the data is output to SO. LE25LB643 8CLK Add ...
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... The data can be read by the status register read command at any time. Figure 5 Status Register Read CS SCK SI SO LE25LB643 Logic 0 1 Busy (in write operation) 0 Write disabled ...
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... If a write operation has not been performed inside the device because, for instance, the command input for any of the write operations has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. LE25LB643 t WPH ...
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... The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable command (06h). Figure 7 Write Enable CS Mode3 SCK Mode0 8CLK 06h SI (00000110) High Impedance SO LE25LB643 Block Protect Settings Protected Area BP0 0 None 1 1800h to 1FFFh 0 1000h to 1FFFh 1 0000h to 1FFFh Mode ...
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... Write (WRITE) The LE25LB643 enables pages with up to 32bytes to be written. Any number of bytes from 1 to 32bytes can be written within the same sector page (page addresses : A15 to A5). “Figure 9 Write” shows the write timing waveforms, and Figure 12 shows a write flowchart. After the falling CS edge, the command (02H) is input followed by the 16-bit addresses (Add) ...
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... Hardware Data Protection In order to protect against unintentional writing at power-on, the LE25LB643 incorporates a power-on reset function. 8. Software Data Protection This product eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. • When a write command is input and the rising CS edge timing is not in a bus cycle (8CLK units of SCK). ...
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... CS Set status register 05h read command NO Bit 0= “0” ? YES End of status register write *Automatically placed in write disabled state at the end of the status register write. LE25LB643 Write Start 06h 02h Address 1 Address 2 Data 0 Data 1 Data n Write start on rising edge of CS ...
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... Precautions at Power-on In order to protect against unintentional writing, the LE25LB643 incorporates a power-on rest circuit. The following conditions must be met in order to ensure that the power-on reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the write operation. ...