78p2343jat Teridian Semiconductor Corporation, 78p2343jat Datasheet - Page 9
78p2343jat
Manufacturer Part Number
78p2343jat
Description
3-port E3/ds3/sts-1 With Jitter Attenuator
Manufacturer
Teridian Semiconductor Corporation
Datasheet
1.78P2343JAT.pdf
(37 pages)
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REGISTER DESCRIPTION
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be
activated. User may set as many bits as required.
Page 9 of 37
BIT
6:3
7
2
1
0
INPOL
NAME
RSVD
RXER
TXER
JAER
TYPE
R/W
R/W
R/W
R/W
R/O
VALUE
DFLT
--
0
0
1
1
(continued)
2005 Teridian Semiconductor Corporation
Interrupt Pin Polarity Selection:
0 : Interrupt output is active-low
1 : Interrupt output is active-high
Reserved
Jitter Attenuator Error Event:
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
DESCRIPTION
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
78P2343JAT
Rev 2.2
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