xr16m2751 Exar Corporation, xr16m2751 Datasheet - Page 16

• Manufacturer Part Number: xr16m2751
• Description: High Performance Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16M2751
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
N
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
•
•
If using the Auto RTS interrupt:
•
The M2751 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return
LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described
conditions, the M2751 will continue to accept data until the receive FIFO gets full. The Auto RTS function is
initiated when the RTS# output pin is asserted LOW (RTS On).
Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The
hysteresis values for Tables A-C are the next higher and next lower trigger levels in the corresponding table.
F
2.12
2.13
OTE
IGURE
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
: Table-B selected as Trigger Table for
Receive Data
Byte and Errors
9. R
16X or 8X Clock
Auto RTS (Hardware) Flow Control
64 bytes by 11-bit
Auto RTS Hysteresis
(EMSR bit-7)
ECEIVER
wide
FIFO
O
PERATION IN
Receive Data Shift
Register (RSR)
Data FIFO
FIFO
Receive
Receive
Data
Figure 9
AND
A
UTO
Validation
Data falls to
Data Bit
Data fills to
Trigger=16
(
Table 11
Example
RTS F
FIFO
24
8
: - RX FIFO trigger level selected at 16
16
LOW
).
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
(See Note Below)
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Figure
C
ONTROL
bytes
Table 14
10):
M
shows the complete details for the
ODE
Receive Data Characters
RXFIFO1
REV. 1.0.0