xr16m2751 Exar Corporation, xr16m2751 Datasheet - Page 20

• Manufacturer Part Number: xr16m2751
• Description: High Performance Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16M2751
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
The M2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave
feature is included to reduce power consumption when the device is not actively used.
All of these conditions must be satisfied for the M2751 to enter sleep mode:
The M2751 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The M2751 resumes normal operation by any of the following when PowerSave mode is disabled (pin 12 at
ground):
If the sleep mode is enabled and the 2751 is awakened by one of the conditions described above, an interrupt
is issued by the 2751 to signal to the CPU that it is awake. The lower nibble of the interrupt source register
(ISR) will read a value of 0x1 for this interrupt and reading the ISR clears this interrupt. Since the same value
(0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode.
The 2751 will return to the sleep mode automatically after all interrupting conditions have been serviced and
cleared. If the 2751 is awakened by the modem inputs, a read to the MSR is required to reset the modem
inputs. In any case, the sleep mode will not be entered while an interrupt is pending from channel A or B. The
2751 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
2751 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on
current can be up to 100 times more. If not using the PowerSave feature, then an external buffer would be
required to keep the address and data bus lines from toggling or floating to achieve the low current. But if the
PowerSave feature is enabled (pin 12 connected to VCC), this will eliminate the need for an external buffer by
internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that
could cause wasteful power drain. The 2751 enters PowerSave mode when pin 12 is connected to VCC and
the 2751 is in sleep mode (see Sleep Mode section above).
Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:
The 2751 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem inputs)
and all interrupting conditions have been serviced and cleared. The 2751 will stay in the PowerSave mode of
operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to GND.
2.19
2.19.1
2.19.2
■
■
■
■
■
■
■
■
■
no interrupts pending for both channels of the 2751 (ISR bit-0 = 1)
sleep mode of both channels are enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pins are idling HIGH
a receive data start bit transition (HIGH to LOW)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
a receive data start bit transition (HIGH to LOW)
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
Sleep Mode with Wake-Up Indicator and PowerSave Feature
Sleep Mode
PowerSave Feature
page
43. If the input lines are floating or are toggling while the 2751 is in sleep mode, the
20
REV. 1.0.0