xr16m780 Exar Corporation, xr16m780 Datasheet - Page 40
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xr16m780
Manufacturer Part Number
xr16m780
Description
1.62v To 3.63v High Performance Uart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16M780.pdf
(58 pages)
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XR16M780
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[6]: Independent BRG enable
•
•
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0]. .
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See
4.14
4.15
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[7]
0
0
1
1
Trigger Level Register (TRG) - Write-Only
RX/TX FIFO Level Count Register (FC) - Read-Only
DLD[5]
DLD[6]
0
0
1
0
1
1
0
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
T
ABLE
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
T
ABLE
Table
14: S
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses same BRG.
Transmitter and Receiver uses same BRG.
15: BRG S
AMPLING
12.
DLD[4]
40
X
0
1
R
ATE
ELECT
S
ELECT
BRG
Table 14
S
AMPLING
16X
8X
4X
R
below.
ATE
REV. 1.0.0