xr16v2550im Exar Corporation, xr16v2550im Datasheet

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xr16v2550im

Manufacturer Part Number
xr16v2550im
Description
High Performance Duart With 16-byte Fifo
Manufacturer
Exar Corporation
Datasheet

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MAY 2007
GENERAL DESCRIPTION
The XR16V2550
universal asynchronous receiver and transmitter
(UART) with 16 bytes TX and RX FIFOs. The device
operates from 2.25 to 3.6 volts with 5 Volt tolerant
inputs and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16C2550. The V2550 register set
is compatible to the ST16C2550 and the XR16L2550.
It supports Exar’s enhanced features of selectable
FIFO trigger level, automatic hardware (RTS/CTS)
and software flow control, and a complete modem
interface. Onboard registers provide the user with
operational status and data error flags. An internal
loopback
Independent programmable baud rate generators are
provided in each channel to select data rates up to 16
Mbps at 3.3 Volt with 4X sampling clock. The V2550
is available in 48-pin TQFP and 32-pin QFN
packages.
N
APPLICATIONS
Exar
F
OTE
IGURE
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
RXRDYA#
RXRDYB#
TXRDYA#
TXRDYB#
: 1 Covered by U.S. Patent #5,649,122
Corporation 48720 Kato Road, Fremont CA, 94538
D7:D0
1. XR16V2550 B
A2:A0
CSA#
CSB#
Reset
IOW#
IOR#
INTA
INTB
capability
1
(V2550) is a high performance dual
allows
8-bit Data
LOCK
Interface
Bus
D
system
IAGRAM
diagnostics.
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
UART
(510) 668-7000
Regs
BRG
(same as Channel A)
* 5 Volt Tolerant Inputs
FEATURES
UART Channel B
Crystal Osc/Buffer
UART Channel A
2.25 to 3.6 Volt Operation
5 Volt Tolerant Inputs
Pin-to-pin compatible to ST16C2550, XR16C2550
and XR16L2550 in the 48-TQFP package
Two independent UART channels
Device Identification and Revision
Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
48-TQFP and 32-QFN packages
TX & RX
16 Byte RX FIFO
16 Byte TX FIFO
Register set compatible to XR16L2550
Data rate of up to 16 Mbps at 3.3 V, and 12.5
Mbps at 2.5 V with 4X sampling rate
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 16 bytes
Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
FAX (510) 668-7017
ENDEC
IR
XR16V2550
GND
XTAL1
XTAL2
2.25 to 3.6 Volt VCC
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
www.exar.com
REV. 1.0.2

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xr16v2550im Summary of contents

Page 1

MAY 2007 GENERAL DESCRIPTION 1 The XR16V2550 (V2550 high performance dual universal asynchronous receiver and transmitter (UART) with 16 bytes TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and ...

Page 2

... UT SSIGNMENT RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# NC RXB RXA TXA TXB CSA# CSB# ORDERING INFORMATION ART UMBER XR16V2550IL32 XR16V2550IM 48-Lead TQFP XR16V2550 6 48-pin TQFP XR16V2550 4 21 32-pin QFN ...

Page 3

REV. 1.0.2 PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP N AME DATA BUS INTERFACE ...

Page 4

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA CTSA DTRA# ...

Page 5

REV. 1.0.2 Pin Description 32-QFN 48-TQFP N AME RTSB CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 10 13 ...

Page 6

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16V2550 (V2550) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data ...

Page 7

REV. 1.0.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The V2550 data interface supports the Intel compatible types ...

Page 8

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO registers, but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1. CSA 2.6 Channel A and B Internal Registers Each ...

Page 9

REV. 1.0.2 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through 22. ...

Page 10

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO at 3.3V with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.10 Programmable Baud Rate Generator with ...

Page 11

REV. 1.0 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) 400 3750 2400 625 ...

Page 12

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.11 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with ...

Page 13

REV. 1.0 IGURE RANSMITTER PERATION IN Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg.) Auto Software Flow Control 16X Clock (DLD[5:4]) 2.12 Receiver The receiver ...

Page 14

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO IGURE ECEIVER PERATION IN NON 16X lock ( D LD[5: eceive Data Byte LSR bits and Errors IGURE ...

Page 15

REV. 1.0.2 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...

Page 16

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 ...

Page 17

REV. 1.0.2 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the V2550 will halt transmission (TX) as soon as ...

Page 18

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.18 Infrared Mode The V2550 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a ...

Page 19

REV. 1.0.2 2.19 Sleep Mode with Auto Wake-Up The V2550 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied ...

Page 20

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.20 Internal Loopback The V2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions ...

Page 21

REV. 1.0.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the V2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set ...

Page 22

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO . T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR ...

Page 23

REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable XON1 RD/WR Bit ...

Page 24

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V2550 in the FIFO polled mode of operation. Since ...

Page 25

REV. 1.0.2 IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from ...

Page 26

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...

Page 27

REV. 1.0.2 FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers (the receive shift register is ...

Page 28

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select The length ...

Page 29

REV. 1.0.2 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR ...

Page 30

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO MCR[2]: IrDA RX Inversion or OP1# (legacy term) When Infrared mode is enabled (MCR[6]=1 and EFR[4]=1), this bit selects the idle state of the encoded IrDA data. In internal loopback mode, this bit ...

Page 31

REV. 1.0.2 LSR[1]: Receiver Overrun Error Flag • Logic overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the ...

Page 32

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO MSR[1]: Delta DSR# Input Flag • Logic change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A ...

Page 33

REV. 1.0.2 4.11 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL is a 16-bit value. Then the value is ...

Page 34

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT ...

Page 35

REV. 1.0.2 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled ...

Page 36

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO T 15: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not ...

Page 37

REV. 1.0.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (32-QFN) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS -40 +85 ...

Page 38

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS -40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock Time Period ECLK T Address Setup Time AS ...

Page 39

REV. 1.0 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI# HIGH PERFORMANCE DUART ...

Page 40

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO F 15 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING ...

Page 41

REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR ...

Page 42

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO F 19 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data ...

Page 43

REV. 1.0 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# (Loading ...

Page 44

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...

Page 45

REV. 1.0.2 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 mm) Note: The control dimension is in millimeter. SYMBOL HIGH PERFORMANCE DUART WITH 16-BYTE FIFO INCHES MILLIMETERS MIN ...

Page 46

... Updated "AC electrical characteristc" table and pin description table. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...

Page 47

REV. 1.0.2 GENERAL DESCRIPTION................................................................................................ 1 A .............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16V2550 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ............................................................................................................................... 2 ORDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 ...

Page 48

XR16V2550 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER ...

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