xr16v2651im Exar Corporation, xr16v2651im Datasheet - Page 25
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xr16v2651im
Manufacturer Part Number
xr16v2651im
Description
High Performance Duart With 32-byte Fifo And Powersave
Manufacturer
Exar Corporation
Datasheet
1.XR16V2651IM.pdf
(51 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16v2651im-F
Manufacturer:
Exar Corporation
Quantity:
10 000
REV. 1.0.2
SEE”RECEIVER” ON PAGE 15.
SEE”TRANSMITTER” ON PAGE 13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the selected trig-
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
ger level. It will be cleared when the FIFO drops below the selected trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
XON1 RD/WR
XON2 RD/WR
N
EFR
R
AME
10: INTERNAL REGISTERS DESCRIPTION.
EG
RD/WR
W
R
EAD
RITE
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
/
Enable
B
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
-7
Enable
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
-6
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
IT
-5
25
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
DLD
IT
-4
S
HADED BITS ARE ENABLED WHEN
B
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
B
ware
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
-2
B
ware
Soft-
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
-1
EFR B
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
IT
XR16V2651
-0
IT
-4=1
LCR=0xBF
C
OMMENT