xr16c850im Exar Corporation, xr16c850im Datasheet - Page 14

• Manufacturer Part Number: xr16c850im
• Description: Uart With 128-byte Fifos And Infrared Irda Encoder/decoder
• Manufacturer: Exar Corporation

XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
The UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter. The prescaler is
controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides
this clock by a programmable divisor between 1 and (2
rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG
divisor (DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG
must be programmed during initialization to the operating data rate.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
2.11
O
UTPUT
MCR Bit-7=1
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Programmable Baud Rate Generator
Data Rate
F
T
IGURE
XTAL1
XTAL2
ABLE
O
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
UTPUT
Table 4
8. B
4: T
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
AUD
400
Data Rate
Crystal
Buffer
Osc/
shows the standard data rates available with a 14.7456 MHz crystal or external
R
ATE
G
Clock (Decimal)
D
ENERATOR
CLKSEL = GND
CLKSEL = VCC
IVISOR FOR
Initialization or
During
Reset
2304
384
192
96
48
24
12
6
4
2
1
16x
14.7456 MH
D
14
Divide by 4
Divide by 1
Prescaler
Prescaler
IVISOR FOR
16
Clock (HEX)
-1) to obtain a 16X sampling clock of the serial data
900
180
C0
0C
60
30
18
06
04
02
01
MCR Bit-7=0
MCR Bit-7=1
Z CRYSTAL OR EXTERNAL CLOCK
16x
(default)
V
Baud Rate
DLL and DLM
Generator
ALUE
P
Registers
Logic
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
Rate Clock to
and Receiver
V
Transmitter
Sampling
ALUE
P
ROGRAM
16X
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
xr
D
E
REV. 2.3.1
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)