xr16c850im Exar Corporation, xr16c850im Datasheet - Page 15

• Manufacturer Part Number: xr16c850im
• Description: Uart With 128-byte Fifos And Infrared Irda Encoder/decoder
• Manufacturer: Exar Corporation

xr
REV. 2.3.1
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
2.12
2.12.1
2.12.2
2.12.3
Transmitter
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
F
IGURE
16X Clock
9. T
Data
Byte
RANSMITTER
Transmit Shift Register (TSR)
O
PERATION IN NON
Transmit
Register
Holding
(THR)
15
-FIFO M
THR Interrupt (ISR bit-1)
ODE
2.97V TO 5.5V UART WITH 128-BYTE FIFO
Enabled by IER bit-1
M
S
B
TXNOFIFO1
L
S
B
XR16C850