xr16c2550ip Exar Corporation, xr16c2550ip Datasheet
xr16c2550ip
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xr16c2550ip Summary of contents
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JANUARY 2005 GENERAL DESCRIPTION The XR16C2550 (2550) is asynchronous receiver and transmitter (UART). The XR16C2550 is an improved version of the PC16550 UART with higher operating speed and faster access times. The 2550 provides enhanced UART functions with 16 ...
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... D7 9 RXB 10 RXA 11 XR16C2550 TXRDYB# 12 44-pin PLCC TXA 13 TXB 14 OP2B CSA# CSB# 17 ORDERING INFORMATION ART UMBER ACKAGE XR16C2550IP 40-Lead PDIP XR16C2550IJ 44-Lead PLCC XR16C2550IM 48-Lead TQFP 36 RESET 35 DTRB DTRA RTSA OP2A RXRDYA INTA ...
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REV. 1.0.1 PIN DESCRIPTIONS Pin Description 40-PDIP 44-PLCC 48-TQFP N AME DATA BUS INTERFACE ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO Pin Description 40-PDIP 44-PLCC 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 11 13 RXA 10 11 RTSA CTSA# 36 ...
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REV. 1.0.1 Pin Description 40-PDIP 44-PLCC 48-TQFP N AME DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 16 18 XTAL2 17 19 RESET 35 39 VCC ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16C2550 (2550) integrates the functions of two 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The ...
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REV. 1.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2550 data interface supports the Intel compatible ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.4 Channel A and B Internal Registers Each UART channel in the 2550 has a standard register set for controlling, monitoring and data loading and unloading. The configuration register set is compatible ...
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REV. 1.0.1 2.7 Crystal Oscillator or External Clock Input The 2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F To obtain maximum data rate necessary to use full rail swing on the clock input. See external clock operating frequency over power supply voltage chart in F IGURE Requires ...
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REV. 1.0.1 The 2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock 16 ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO IGURE RANSMITTER Data Byte 16X Clock 2.9.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR ...
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REV. 1.0.1 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.11 Internal Loopback The 2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...
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REV. 1.0.1 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The registers are ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO . T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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REV. 1.0.1 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 4.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status ...
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REV. 1.0.1 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select The ...
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REV. 1.0.1 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR bit-5 selects the forced parity format. • LCR[5] = logic 0, parity is not forced (default). • LCR[5] = logic 1 and LCR[4] = ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO MCR[3]: OP2# Output / INT Output Enable This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general purpose ...
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REV. 1.0.1 LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO MSR[7]: CD Input Status Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may ...
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REV. 1.0.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) Thermal Resistance (40-PDIP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS U : TA=-40 ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS O O TA=-40 + 2.97V ARAMETER YMBOL - Crystal Frequency CLK Clock Pulse Duration OSC External Clock Frequency T Address Setup ...
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REV. 1.0 12 IGURE IMING ALUES - IGURE LOCK IMING CLK EXTERNAL CLOCK 2.97V TO 5.5V DUART ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ATA US ...
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REV. 1.0 IGURE ATA US RITE IMING A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 18 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* T WRI TXRDY# IOW# (Loading data into ...
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REV. 1.0.1 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL α 2.97V TO 5.5V DUART WITH ...
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XR16C2550 2.97V TO 5.5V DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.0.1 PACKAGE DIMENSIONS (40 PIN PDIP Seating Plane L B Note: The control dimension is the millimeter column SYMBOL α 2.97V TO ...
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... Clarified AC Electrical Characteristics. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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TO 5.5V DUART WITH 16-BYTE FIFO 5.0 TABLE OF CONTENTS GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS F ..................................................................................................................................................... 1 EATURES F 1. XR16C2550 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN ...
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XR16C2550 REV. 1.0.0 T 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 24 ABLE ABSOLUTE MAXIMUM RATINGS...................................................................................25 PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) ................25 ELECTRICAL CHARACTERISTICS ................................................................................ LECTRICAL HARACTERISTICS LECTRICAL ...