xr16c2550ip Exar Corporation, xr16c2550ip Datasheet - Page 19
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xr16c2550ip
Manufacturer Part Number
xr16c2550ip
Description
Dual Uart With 16-byte Transmit And Receive Fifos
Manufacturer
Exar Corporation
Datasheet
1.XR16C2550IP.pdf
(38 pages)
xr
REV. 1.0.1
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•
•
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.5
4.6
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FIFO Control Register (FCR) - Write-Only
Line Control Register (LCR) - Read/Write
T
B
FCR
ABLE
IT
0
0
1
1
-7
9: R
B
FCR
IT
0
1
0
1
ECEIVE
-6
1 (default)
FIFO T
R
T
L
RIGGER
ECEIVE
EVEL
14
4
8
19
RIGGER
16C550, 16C2552,
16C554, 16C580 com-
patible.
L
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
C
EVEL
OMPATIBILITY
Table 9
S
ELECTION
shows the complete selections.
XR16C2550