xr16c2550ip Exar Corporation, xr16c2550ip Datasheet - Page 3

• Manufacturer Part Number: xr16c2550ip
• Description: Dual Uart With 16-byte Transmit And Receive Fifos
• Manufacturer: Exar Corporation

Pin Description
xr
REV. 1.0.1
PIN DESCRIPTIONS
DATA BUS INTERFACE
RXRDYA#
TXRDYA#
TXRDYB#
CSA#
CSB#
N
IOW#
IOR#
INTB
INTA
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
AME
40-PDIP
P
26
27
28
21
18
14
15
30
29
IN
8
7
6
5
4
3
2
1
-
-
-
#
44-PLCC
P
29
30
31
24
20
16
17
33
32
34
12
IN
9
8
7
6
5
4
3
2
1
#
48-TQFP
P
26
27
28
48
47
46
45
44
19
15
10
30
29
43
31
IN
11
3
2
1
6
#
T
YPE
IO
O
O
O
O
O
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on the
rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel A. See
If it is not used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides
the RX FIFO/RHR status for receive channel A. See
not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output pro-
vides the TX FIFO/THR status for transmit channel B. See
If it is not used, leave it unconnected.
3
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
D
ESCRIPTION
Table
XR16C2550
2. If it is
Table
Table
2.
2.