xr16c2552ij Exar Corporation, xr16c2552ij Datasheet - Page 19

• Manufacturer Part Number: xr16c2552ij
• Description: 2.97v To 5.5v Dual Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.6
4.7
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FIFO Control Register (FCR) - Write-Only
Line Control Register (LCR) - Read/Write
B
FCR
IT
0
0
1
1
-7
T
ABLE
B
FCR
IT
0
1
0
1
-6
9: T
RANSMIT AND
1 (default)
R
T
RIGGER
L
ECEIVE
EVEL
14
4
8
Table-A. 16C550, 16C2550, 16C2552, 16C554,
16C580 compatible.
R
ECEIVE
19
FIFO T
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
RIGGER
C
OMPATIBILITY
L
EVEL
S
ELECTION
XR16C2552